11 Replies Latest reply on Oct 1, 2015 11:00 AM by jc2048

    FPGA Design Consideration

    hawktalon

      Hi, I'm very new to FPGA. Most of what I did was PIC and Atmel microcontrollers. I want to know about the design consideration of implementing an FPGA into a system. How do you pick the suitable FPGA to suit your needs? I know there are specifications such as number of logic elements, PLLs, multiplier and such but you will never know how much of those you will need until you finish the vhdl and compile it. Correct me if I'm wrong but I'm pretty sure the hardware has to be finalized before the vhdl codes are done in a general development process.

       

      Also, I see that there are a few companies making FPGA. Namely Xillinx, Altera, Lattice etc. What are the differences between their product? Most of what I can search online talks about their development IDEs in terms of which one has free tools or which company has IP restrictions. It's hard for a beginner like me to make sense of what Cyclone offers compared to Spartan and such.

       

      Third question is how do you objectively quantify and compare the performance between FPGAs? Assuming they all run at the same clock. Since they are all essentially doing the same thing and is functionally the same when loaded with the same vhdl code. How do they fare against each other in terms of efficiency, speed and what not? Googling around I only find people comparing them with GPUs and CPUs. Companies advertising their product using vague and very general descriptions doesn't help at all.

       

      Sorry if these are very newb questions but I am a newb trying to learn FPGA. My college provides FPGA courses which I am now just starting but they only teach how to write vhdl. There are no info on hardware considerations or even how to set up a FPGA chip. Thanks in advance!

        • Re: FPGA Design Consideration
          John Beetem

          That's a lot of material to cover, but I'll try to tackle a few items.

           

          First, it's unfortunate that your college only does VHDL.  I personally prefer Verilog, which is more concise and IMO easier to write and understand.  Verilog is based on C.  VHDL is based on Ada.

           

          Second, there's a huge spectrum of FPGA offerings so which you choose depends on what you want to do and how much money you want to spend.  There are cheap ($1 or a few dollars) FPGAs from Lattice -- e.g., the iCE40 family -- with a small number of look-up tables (LUTs).  They're a good alternative to CPLDs, which are now a "mature" technology.  Small FPGAs are good for "glue" logic and various specialized communication interfaces.

           

          Then you have mid-priced ($10s of dollars) FPGAs from Xilinx (Spartan) and Altera (Cyclone), with enough logic, RAM, and arithmetic to do amazing things.  I've mostly used Xilinx and it's my preference at this level.

           

          Then you have expensive FPGAs ($100s to $1000s of dollars) from Xilinx and Altera.  These are mostly for highly-specialized applications like signal/image processing and cryptography that can afford chips like these.

           

          I've always been able to fit customer applications into Spartan chips by using logic resources efficiently.  Xilinx salesmen don't like me.

           

          When I do an FPGA design for a customer, I want to use the cheapest FPGA that will do the job.  However, I also realize that the customer's needs may change and they'll want to do much more with the same hardware, so I choose an FPGA family and package that has a range of FPGA capacities in the same package.  Xilinx Spartan tend to do this well.

           

          To make sure everything fits, I do a preliminary design and synthesize it to make sure it fits the logic and RAM capacity of the FPGA and meets the clock cycle constraint.  Sometimes it's necessary to pipeline a design to meet the clock cycle.  I far prefer to use a relatively slow clock -- say, 33-40 MHz for a Spartan-3A or Spartan-6 -- so that I can fit many levels of logic into a single clock cycle.

           

          For people who are just starting out and want to play with FPGAs without investing much money, I strongly recommend Lattice's iCEstick, which is available in the USA for as little as $22 (though for some reason element14 has it listed for $30, with none available).  A unique feature of the Lattice iCE40 FPGA on iCEstick is that it can be programmed using open-source tools: http://www.element14.com/community/thread/43876/l/project-icestorm-fully-open-source-fpga-tools-for-lattice-ice40.  The tools support Verilog rather than VHDL.

           

          If you have more money to spend, I recommend Gadget Factory's Papilio boards and ValentF(x) LOGI-Pi and LOGI-Bone.  They bring out lots of I/O and some of the boards have external SRAM or SDRAM.

           

          FPGA software and chip interfacing have steep learning curves.  I recommend using an existing board like iCEstick or Papilio so you don't need to consider details like how to configure FPGAs.  The Xilinx and Altera design software packages are huge and will take a lot of time to get working.  There are tutorials out there -- Gadget Factor is a good place to start.  The open-source IceStorm for Lattice iCE40 has a much simpler learning curve, but has minimal documentation.  You'll need a GNU/Linux box with a GCC compiler that supports C++11 to compile and run the IceStorm tools.

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            • Re: FPGA Design Consideration
              hawktalon

              Hi John,

               

              first of all, thanks for responding! You have certainly cleared up quite alot of questions I had!

               

              My college's syllabus for VHDL is probably ancient at this time. We're still using Altera Quartus II 8.1 for some unknown reason. I've got v15 running in Ubuntu since ModelSim for some reason doesn't work in Windows 10. I will look into Verilog since if it is based on C, that will be much easier for me to work with since I am more familiar with it.

               

              My real question is targeted at the very beginning of the development process. Say you have a project, for example a cryptocurrency mining device. For the sake of the discussion, the target for the device is "x" amount of performance at "y" cost. Let's leave power consumption out of the equation for now. Where do you start? Which family/brand of FPGA would you pick? What are the specification needed for the FPGA (assuming you have not started on the VHDL/Verilog)? How do you know which FPGA could deliver what kind of performance?

               

              Also, I am currently trying to acquire a FPGA dev board to learn. I think my college has some sort of partnership with Altera since we have ample supplies of DE2 boards and everything is taught in Quartus. But since I am going to graduate soon, I will need to buy something to continue experimenting with. I am thinking of getting one of the DE0 nano boards from Terasic. They seem to offer quite alot of specifications(sorry if my judgement is too newb) for the money. Here are some links.

              http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=593&PartNo=1

              http://my.element14.com/terasic-technologies/p0082/ep4ce22f17c6n-de0-nano-dev-kit/dp/2076463

               

              Another thing is, is there any barriers to switching between companies? For example, I am now currently more familiar with Altera but I might want to switch to Xillinx products in the future. How hard would it be to make the switch?

               

              Again, thank you so much for replying!

                • Re: FPGA Design Consideration
                  John Beetem

                  Patrick Wong wrote:

                   

                  My real question is targeted at the very beginning of the development process. Say you have a project, for example a cryptocurrency mining device. For the sake of the discussion, the target for the device is "x" amount of performance at "y" cost. Let's leave power consumption out of the equation for now. Where do you start? Which family/brand of FPGA would you pick? What are the specification needed for the FPGA (assuming you have not started on the VHDL/Verilog)? How do you know which FPGA could deliver what kind of performance?

                   

                  Another thing is, is there any barriers to switching between companies? For example, I am now currently more familiar with Altera but I might want to switch to Xillinx products in the future. How hard would it be to make the switch?

                  Once you have VHDL or Verilog design, it's usually pretty easy to switch between similar FPGAs from different vendors.  If you're using a feature like Distributed RAM or DSP processing elements like multiply-accumulate blocks, you might need to tweak the source code so the synthesizer does the right thing.

                   

                  Getting back to the original question, guessing which FPGA to use is mostly something that comes with experience.  Sometimes you can get an idea of what is possible by looking at the IP ("Intellectual Property") offered by an FPGA vendor and seeing what size and family FPGA is needed for a given design.  For example, both Xilinx and Altera have "soft processors" which are CPUs implemented in FPGA logic.  You can see how much logic each of them require, and what CPU performance you get for various FPGAs.

                   

                  Another good way to do this is to write VHDL/Verilog for key parts of your application and run them through the vendor tools to see what performance you can get for various FPGA families.  If it works with a low-cost Spartan or Cyclone, go for it.  If it requires a larger chip or a faster (and more expensive) family, then you have to decide if the extra cost is worth it or review your design to see if there's something clever you can do to make it fit in a cheaper chip.  Working through these kinds of trade-offs and coming up with ingenious solutions is the essence of engineering (the word is based on "ingenuity").

                   

                  When selecting an FPGA family, I usually go with a family I'm already familiar with.  So recent designs have been mostly Xilinx Spartan-3A, which is a very nice family.  However, my most recent design is Spartan-6, since Spartan-3A is no longer the "sweet spot" and will go end of life in the near future.  Spartan-6 is now the "sweet spot".  It's a more complex architecture, but also more powerful than Spartan-3A and has wonderful distributed RAM capability.

                   

                  Some of my designs need a small FPGA.  I used to use CPLDs for this, but they have limited flip-flops and are starting to go end of life.  I've recently used Actel (now MicroSemi) ProASIC3, which are nice chips but rather expensive.  For a small FPGA, I'd check out Lattice iCE40.

                   

                  If you're already familiar with Altera, go ahead and keep using them.  michaelkellett is our Altera and VHDL expert and recently wrote a nice 'blog about a cheap Cyclone board: Cheap Entry into FPGA

                    • Re: FPGA Design Consideration
                      michaelkellett

                      I wouldn't consider myself to be an Altera expert but I do use VHDL quite a bit.

                       

                      I've been away so others have covered the key points.

                       

                      You don't really suffer from vendor lock in on simple FPGA hardware but as soon as you buy any serious IP (dev tools or IP to run on the chips) then the lock-in effect builds up very quickly. At the high end the device architecture drives the design much more and changing FPGA vendors is very expensive.

                       

                      As you would expect I would advise you to stick with VHDL (but it's best to know both).

                       

                      Your cheapest entry is to buy a little Chinese board with an Altera Cyclone II on it and a "usb-blaster" clone - they pair will cost you about £20 and the design tools are free.

                       

                      When you have a specific project you need to choose the target device, based on the demands of the project - and these are often non technical, eg your employer has invested in tools for X, so of course that's the way you go unless the parts are completely unsuitable.

                       

                      MK

                  • Re: FPGA Design Consideration
                    Jan Cumps

                    On the tutorial part, there's also the very good VHDL handbook (and a list of FPGA projects he did, with source code) from hamsternz.

                    FPGA course - Hamsterworks Wiki!

                     

                     

                    I'm using a jack.gassett 's  Papilio Pro (Papilio FPGA Platform) as my FPGA training board. devbisme2 's Xula and Xula-2 are also excellent: http://www.xess.com/

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                  • Re: FPGA Design Consideration
                    pcmorris

                    Right, there's a lot covered already so I'll try not to repeat anything. Forgive me if I do.

                     

                    I would highly recommend not just writing your VHDL, this is a really bad habit I get into when I'm at home and I just want to get to the good stuff. In industry you'd draw out the system, it might just be a block diagram showing how to get from the inputs to the conclusion. Determine approximately how much data you need to move between the blocks, how you want to manipulate that data and how fast you need to do it to achieve your requirement. If you know for example that you want to take in two lots of 16 bits and multiply them together 20 times in parallel you should be able to determine approximately how many logic elements your going to use before you even being coding which will help you determine how many flip flops you need from a device when your designing the hardware. Equally, if you know you need a pci interface, then you know the timing specification you need to achieve on the chip, not all chips can achieve this frequency so this will again focus your decision. The key is contingency, your not going to be spot on with your sizing estimates and ideally you don't want to be running the clock at the boundary of the chips performance so take your numbers and add a bit before you seriously look to buy.

                     

                    With regards to choice of vendor, there is nothing to stop you writing VHDL in notepad and using just the vendors synthesis tools. Yes there is a learning curve with the toolset but if you write VHDL which conforms to the standards then you should not have a problem moving between vendors unless as previously mentioned you are using vendor specific macros. I would probably steer clear of ProASIC range for development at home, Xilinx and Altera are flash based tech which is great for home development, some of the Microsemi line work in a different way which is geared towards other applications.

                     

                    The DE0 is a nice looking development board, but I couldn't speculate whether it's capable for this kind of work. Best of luck, keep us all posted on how it goes.

                    • Re: FPGA Design Consideration
                      hawktalon

                      Thanks everyone for replying! There are so many useful infos here which one would certainly not find in any online articles or academic books. I don't want to pick any one of the replies as "correct answer" for fear of the thread being locked down (or they don't do it this way here? correct me if im wrong) preventing further addition to the useful infos here. It is best to collect all the info in one place to ease newcomers to pick up FPGA.

                       

                      So to recap the solutions stated as of writing/typing:

                      • Check the minimum requirements by calculating based on the number of bits need to be processed and at what speed. Should be able to get a rough guess on number of logic elements.
                      • If need to be PCI based, check the speed of the gates for compliance.
                      • Try out the vendor's synthesis tool.
                      • If your company has already invested in this equipment and that resources, the choice has already been made for you.

                       

                      I am only a college student just starting to learn about FPGA so don't expect me to come up with great projects anytime soon lol.. But I am interested in this wonderful piece of technology which enables the creation of a system of discrete logics using codes. Lastly, I really can't thank everyone enough for contributing here. Hope that this thread would be a good source of information for those interested!

                      • Re: FPGA Design Consideration
                        hawktalon

                        Ok, one more question. How do you differentiate the chips from the vendors in terms of the design of the chips themselves not the IDEs. What makes Xillinx/Altera/Lattice chips different from each other?

                          • Re: FPGA Design Consideration
                            michaelkellett

                            At the beginner level it doesn't matter much - simple things like power, price, packages, ip support and availability are more important than the core architecture.

                            You'll only fully understand and care about the differences as you become more experienced.

                            You can read a lot of interesting material on the Xilinx and Altera websites about the high end stuff.

                            Lattice are much more in to the low end small devices.

                            Although I've been FPGA-ing since Xilinx made the first 64 LUT device I wouldn't be able to give you a good analysis of the relative merits of Altera and Xilinx high end devices, quite simply because I don't work in that area.

                             

                            Things that might sway some people are:

                            Xilinx have a fairly low cost C -> FPGA tool (it isn't quite C and it isn't 100% automatic),

                            Altera have just announced a new RAD hard device for space applications,

                            Lattice ICE40 parts use hardly any power (I just measured the core current on an ICE40 HX8 running  a data acquisition application at 400k samples/second and using 50MHz primary clock at 3.5mA)

                             

                            MK

                            • Re: FPGA Design Consideration
                              John Beetem

                              Patrick Wong wrote:

                               

                              Ok, one more question. How do you differentiate the chips from the vendors in terms of the design of the chips themselves not the IDEs. What makes Xillinx/Altera/Lattice chips different from each other?

                              As michaelkellett pointed out, this will become more important as you gain experience and start looking for ways to optimize designs.  But here's some of the things I look for...

                               

                              You can get a quick overview of an FPGA architecture by looking at the family's data sheet, technical reference, or user guide.  Take a look at the basic cell architecture.  Most FPGAs are based on k-input look-up tables (LUTs) which can realize any k-input logic function.  However, the value of "k" varies.  I've mostly used Xilinx Spartan-II, -IIE, -3A, and -3E which have 4-input LUTs.  The newer Spartan-6 has 6-input LUTs, which can be used as two 5-input LUTs that share the same input signals.  Actel (now MicroSemi) ProAsic3 have the equivalent of 3-input LUTs.  I've found that 4-input LUTs work quite well, but that 3-input LUTs require far more LUTs to realize a design, and you'll get more levels of logic and thus poorer performance.  6-input LUTs are kind of overkill, but have a big advantage for distributed RAM (see below).

                               

                              A logic cell also has a flip-flop or latch.  Here you get lots of differentiation.  For example, the Xilinx Spartan parts I've used have a flip-flop that can be either an edge-triggered FF (either clock edge) or level-sensitive latch (either clock level).  However, Lattice iCE40 only has edge-triggered FFs.  Some families require groups of FFs to share the same clock edge.  This is not a problem if your design has a single clock (very highly recommended) but if you have multiple clocks there's a potential for placement to fail.

                               

                              Some families (Xilinx Spartan) let you use the LUT and FF independently, which means you have lots of extra FFs lying around which can be useful for pipelining.  Others (iCE40) directly connect the FF to the LUT, so you can't use the FF independently.  Still others (ProAsic3) let you use a cell as a LUT or a FF, but not both.  This can burn through cells quickly in a design with lots of FFs.

                               

                              Some logic families (Spartan) let you use a LUT as a small RAM, a concept called "Distributed RAM" as opposed to "Block RAM" which are larger blocks of dedicated RAM.  Distributed RAM can be incredibly useful for some designs.  For example, Spartan-IIE/3A/3E let you use a 4-input LUT as a 16x1 RAM, or two together as a 32x1 RAM or a 16x1 dual-port RAM.  I use this to time-multiplex combinational logic with 16 different copies of the "state" instead of having to implement 16 copies of the combinational logic.  Seymour Cray used this trick with the CDC 6600 peripheral processors.

                               

                              The Lattice iCE40 doesn't have distributed RAM.  The Xilinx Spartan-6 has very powerful distributed RAM thanks to its 6-input LUTs, which lets you easily multiplex 32 virtual copies of a block of logic.

                               

                              Cells may also have built-in carry chain logic and 2:1 multiplexers for combining the outputs of adjacent LUTs to form large multiplexers and other logic functions.

                               

                              Then there are other features like Block RAM, multiply/accumulate blocks for DSP, and PLLs for clock control.  Making use of these restricts your ability to switch between FPGA families, but they can create powerful functionality in a low-cost FPGA.

                            • Re: FPGA Design Consideration
                              jc2048

                              This is an interesting thread and I'd like to add a few (rather random) thoughts. Note, though, that I haven't done anything with FPGAs for about 5 years now, so some of this may be a bit out of date.

                               

                              I worked with Spartan 3 parts using VHDL.

                               

                              Speed. The headline speed on the datasheet is for a very simple counter. You won't create a real design to operate that fast. The way to get a feel for the realisable speeds you can achieve is to knock up some trial designs and look at the max clock speed that gets reported. It's not easy to give you an guide because it depends so much on how you code and how well that maps onto the hardware, the nature of the design and what you're trying to do, how much of the device resources you're using, and so on.

                               

                              The DL in VHDL stands for Description Language. You are describing the hardware. You really do need to understand the underlying hardware to code efficiently. If you approach it as a simple programming exercise you'll end up with very bloated designs that only run slowly.

                               

                              Watch out for implied memory.

                               

                              Once you've done a few designs, you'll find that you can go a long way on cut-and-pasting. I got so that my start point for a new design was generally something I'd already done that was similar.

                               

                              The synthesis software works very efficiently if the design is sparse [say up to 50%-60% utilisation of resources], but as you cram more and more into your design you'll find it gets harder and harder for it to complete, even though in theory there are resources still available. If you are working commercially, and don't need to shave every last penny off your costs but do need to get designs out quickly and efficiently, give yourself plenty of capability in hand. One nice feature of the Spartan parts was having 2 or 3 different densities of device available in the same footprint package - knowing that there was a higher density device available that could go on my board was reassuring early on when I wasn't very confident about estimating the logic and memory resources that I would need.

                               

                              Constraints (timing and placement) seem like a good idea but can be counterproductive. I had a design where I needed a very small part of my design to operate very quickly. I tried tying down the logic blocks concerned and put timimg constraints on the signals and it always did worse than the unconstrained synthesis. The programmers at Xilinx knew their chips much better than I did and me tying them down was just getting in the way. [But do experiment - that's the kind of thing that can change or you might have a flair for it that I don't]

                               

                              The Xilinx design software has a viewer to show you how the synthesis has arranged everything internally. Use it as you gradually build up a design and you'll get a feel for how the synthesis places everything. It will also show you [with a bit of experimentation on your part] how to organise your IO pins to best work with your internal logic and minimise timing delays.

                               

                              The block RAMs in the Spartan parts turned out to be very useful [though as John Beetem says you're making your design less portable]. Table look-up is very fast - I used them for gamma correction, amongst other things. The RAM can be loaded from configuration data to give a ROM, too, though I usually used the second port to load the table values from an external processor. They were also useful for moving between clock domains [several of the products I worked on involved taking DVI from a computer and processing it, and the dual-port block RAMs enabled me to set up a swinging buffer with different clocks on the two sides].

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