15 Replies Latest reply on Jan 18, 2014 3:57 AM by wachag

    1V Power supply under-powered


      What's the maximum power that can by drawn by the Zynq PL? Has this been tested?

      I have build a large design (80%) that need to runs at 100MHz, but when I program the bitstream to the Zedboard. The Zynq reset a few ms after being DONE.

      Also, I have probed the 1V power supply at C357. After, the PL is DONE, the voltage go down to about 560mV and go back up to 1V probably because the PL resets.

      What could be causing this?

      Is it because the PL draw to much power?

        • I have done some further

          I have done some further analysis on this matter. I have found in the Zedboard user guide that the budgeted ammount of power for the PL is 1.2A on 1V PSU.

          However, using Xilinx Power Analyser, I see that my design can drawn as much as 1.3A. See http://www.louif.com/power_analysis.png .

          Also, to verify that it was the power drawn that made the Zynq reset and not some other design flaw, I added clock gating so that much of the design would not draw power at startup. And indeed, in that case, Linux boots just fine. But still, as soon as I activate the clock in the design, the Zynq resets.

          I measure the voltage on the 1V rail using an oscilloscope during reset. You may see the results here: http://www.louif.com/ADS00001.BMP

          Is there any plan to beef up the 1V PSU so that it can handle a full load? This seems to be like a show-stopper.

          • Confirmed

            I though I'd let you know that I have confirmed this issue.

            I bypassed the 1V power supply by using an external power supply. Now, the design is working and as much as 3A is drawn from the 1V power supply.

            This is much more than the 2A the MAX15021ATI+ (onboard 1V PSU) is capable of.

              • I have the similar issue and

                I have the similar issue and need an external power supply to power the core voltage. Any tips in modifying the board? Where did you cut the wire and connect the jumper wires? Thanks.

                • You are correct that the 1V

                  You are correct that the 1V supply on ZedBoard has a max capacity of 2A. This is shared between all of the 1V requirements on Zynq 7020 -- Vccint, Vccpint, and Vccbram. We estimated what a reasonably aggressive design might do using the tools available at the time which was 13.2 Beta Xilinx Power Estimator. We then added 50% margin to cover any inaccuracies.


                  It is unfortunate that ZedBoard is not capable of supplying what your application requires. If you are willing, I am very interested in correlating what we created in XPE to what your design is doing. Have you analyzed what your design should be drawing in XPE? If so, will you please share it?


                  As changing the 1V supply on ZedBoard would require extensive redesign and we believe it is sufficient for the majority of users, we will not redesign the ZedBoard power supplies.  For those that need more than 2A on the 1V rail, we recommend you use the ZC702 board instead.



                    • Xilinx Power Analyzer

                      Xilinx Power Analyzer calculates that my design will use around 1.2A ( http://www.louif.com/power_analysis.png ). I think this is not considering what the ARM processor is using (0.6A).

                      So, I cannot account for up to 1.2A of power usage. Also, 3A is a peak usage, so it may have been transcient.

                        • I would agree that this

                          I would agree that this screenshot does not include show the PS running -- notice the Vccp___ supplies. Vccpint is only drawing 23 mA. So there is definitely something missing here. Assuming the PS is 0.6A, that extra 1.2A is still a mystery. We have re-analyzed a Zynq 7020 design in the latest 2013.1 XPE with a 80-90% loaded design, and we are still getting ~1.2A, including the PS. I have never known XPE to be more than 20% off. Perhaps we are not including something. Or maybe XPE has a bug this time. Perhaps your design has characteristics that we haven't mapped properly in XPE, such as clock rate, fanout, etc.


                          If you'd like to take a look at our analysis, see the XPE spreadsheet here.




                    • Fix with external power supply

                      I have removed the L5 coil and connected a wire to one of the pad disconnecting the onboard 1V power supply and connecting the wire to the load. The negative wire may be connected to the ground of C357.

                      Check the board schematic and be careful.

                      If you don't do this correctly, you will blow up the board.

                      • recommendation for designing your own Zynq power

                        Hey everybody,

                        I've been talking with Bryan about the power issue and wanted to make a suggestion to the community if you are looking to design your own ZedBoard.  The two outputs of the MAX15021 are capable of 4A and 2A respectively.  In our design we had the 1.5V used to power the DDR running off of LX1 (the 4A output).  Our estimations show that the max expected current draw on the 1.5V rail is 1.5A.  That means that the 2A LX2 output should be sufficient to provide the current needed for the memory.

                        If you design your own board, use the 1uH inductor from the 1.5V supply and just swap the circuits for 1V to the LX1 output and for 1.5V to the LX2 output.  You'll notice that all the components are the same except for the feedback set resistors and the inductor.  You'll need to use the larger current rated inductor on the 1V supply as well, but other than that there are minimal changes.

                        In the meantime, if anyone who has had this issue would be willing to share their ZedBoard design and their XPE output with us it would be greatly appreciated.  I'd like to work with these data points to try and determine where the disconnect is between the tool and the actual current draw.  I'd like to go back to Xilinx to discuss what we've seen, but I need to be able to reproduce the scenario on my bench to be able to accurately describe the problem.

                        • same issue with underpowered vccint

                          Using the zedboard for cryptographic applications, I experienced the power limit on the 1V Vccint and it is really a killer. In this kind of application, you try to fill up the FPGA and to use every clock cycle.

                          I don't want to sound grumpy - I enjoy my zedboard very much - but I do think this limitation should be either corrected or clearly advertised otherwise people might just buy a useless board.

                          • zed board et all

                            Must admit,
                              If I had released the problems and compromises made on the ZED board, such as power and heat dissipation,  I'd have spent the extra money and purchased a ZC702

                            The hours / days of problems do not bode well.

                            • We are very interested in

                              We are very interested in doing more to resolve this issue, possibly even modifying the ZedBoard.


                              Is anyone willing to provide us with their design where you see these failing issues?


                              Has anyone attempted  to correlate their design to an estimate in XPE that they will share? Perhaps we are not being aggressive enough in the way we are setting up XPE.


                              If confidentiality is an issue, I believe we can negotiate an NDA before experimenting with your design. Chris and I both requested more details back in June, but we did not get any designs. Without receipt of a failing design, we are in the position of having to go make something up to try to aggravate this.