5 Replies Latest reply on Mar 2, 2016 9:27 AM by troutchaser

    How to change the interrupt trigger type to "Rising/Falling edge triggered"?

    100prathima

      I have a custom IP on PL generating an interrupt signal.
      I have successfully connected it to an ISR in my code.
      But, the ISR is getting triggered continuously. This is due to default settings to "High level triggered" interrupt.
      I want to change this to "Rising/falling edge triggered".
      I tried calling
      XScuGic_SetPriorityTriggerType(IntcInstancePtr,91,0,3);
      I have only one interrupt and set it to highest priority i.e., 0.
      91 is my Int_Id.
      I read in one of the comments in xscugic.c that setting trigger type to 3 configures the interrupt to rising edge triggered. But it is not happening so.
      Am I missing something?
      Please help me...

        • solved
          100prathima

          Calling XScuGic_SetPriorityTriggerType works!
          There was a continuous triggering because the interrupt pending register was not cleared. I'm not sure why.
          I tried setting the corresponding bit for int_id 91 in the ICDICPR register. It worked.

          • how to implement?
            jenslin

            How did you implement clearing the ICDICPR register? It appears that I am running into the same problem and I'm not sure if I am clearing the pending register properly.

            • Re: how to implement?
              100prathima

              Refer the TRM for the bit position for your Int ID in the ICDICPR.
              Write 1 to that bit location.
              ICDICPR is split into 3 registers based on int ID.
              My int ID was 91. I wrote to ICDICPR3 register.

              I used the following statement in the ISR:
              *(int*)(0xF8F01288) |= 0x08000000;//Clear interrupt pending register at position 91

              • I am facing the same problem,
                jomarm10

                I am facing the same problem, but the interrupt ID is 61, I have searched the documentation of Xilinx and Arm but have not figured what is the exact address I have to write to nor the value and I need some help

                From my system I have that the base address of the device is
                #define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000

                but I would need help in order to understand the documentation and find the offset to add for the interrupt with id 61 and the value to write to that address

                • You might want to take a look
                  troutchaser

                  You might want to take a look at the example and selftest code supplied with the SDK. The location in a typical Vivado installation is:

                   

                  C:/Xilinx/SDK/2015.4/data/embeddedsw/XilinxProcessorIOLip/drivers/

                   

                  Then select one of the peripherals that supports interrupts and look at the seftest and example code. The code for the GIC is there as well.

                   

                  -Gary