5 Replies Latest reply on Mar 28, 2019 3:34 PM by olemi

    How to set routing vias be covered with mask? Always.

    olemi

      This doc describes the process for non-routing vias:

      http://documentation.circuitstudio.com/display/CSTU/PCB_Dlg-Via((Via))_CS

       

      "PCB rules > Routing Via Style" doesn't have Solder Mask Expansion option.

       

      "PCB rules > Solder Mask Expansion" doesn't have vias for the object.

       

      How?

        • Re: How to set routing vias be covered with mask? Always.
          tarribred61

          I suspect you won't be satisfied but here is a complicated way to do it using rules.  For a simpler way see my follow-up post below about using PCB filters. The rules method would change expansion rules on ALL vias but it may be possible to change to be more specific with more effort.

          If you really need to have good control of the rules then you may need to pay for full Altium Designer which has very good editors and logic testing for complex logical statements. Or hope someone will build a separate utility app to manipulate the rule text.

           

          Otherwise, you can manually take control in a painful process.  Hopefully, this will give some readers a clue as to how this works and they can devise a better method.  (Or it will scare them off.)

           

          Open the PCB Rules and Constraints Editor (Home > Design Rules).

          Go to Mask>Solder Mask Expansion and then right mouse click and add New Rule; give it a name like SolderMaskExpansion_vias. Click Apply button.

           

          Observe the column that says Scope.  Is should say "All" or "(All)" for a value.  Change the attributes to a large negative value if you want to tent fully or to whatever you want it to be.  Here I have changed mine to be -10mil.

           

           

          Right mouse click anywhere in the navigation pane for the rules tree and choose Export Rules.

          Pick Solder Mask Expansion rule to select it for export; press OK.

          Choose a place to export the RUL file to rather than the default (maybe a folder named CS_Rule_Sandbox or something.  Name the file something appropriate rather than the generic default.

          Use your favorite text editor to open the filename.RUL file.

           

          For example, this is what I get from the default as the default.

          SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|UNIONINDEX=0|UNIQUEID=ICMNQFCH|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion|ENABLED=TRUE|PRIORITY=2|COMMENT= |DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=4mil¶

           

          If you add another rule then you would get more entries.  Since, we added another rule above I get the following in my editor.  It isn't in a pretty and human readable format but it is in text.

          SELECTION=FALSE|LAYER=UNKNOWN|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|UNIONINDEX=0|UNIQUEID=AATYVYYQ|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion_vias|ENABLED=TRUE|PRIORITY=1|COMMENT= |DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=-10mil¶

          SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|UNIONINDEX=0|UNIQUEID=ICMNQFCH|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion|ENABLED=TRUE|PRIORITY=2|COMMENT= |DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=4mil¶

           

          You can edit the rule scope. Above it would be SCOPE1EXPRESSION=All. Change text All to be IsVia.  You'll also see a SCOPE2EXPRESSION.  This is what AD uses and I don't know if CS will ignore it or use it also.  This can perhaps experimented with it in future.

           

          To make more complex rules you would need to read and understand Altium's rule expressions and how to use AND and OR and parenthesis.

           

          So now my rule expressions are:

          SELECTION=FALSE|LAYER=UNKNOWN|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|UNIONINDEX=0|UNIQUEID=AATYVYYQ|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsVia|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion_vias|ENABLED=TRUE|PRIORITY=1|COMMENT= |DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=-10mil¶

          SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|UNIONINDEX=0|UNIQUEID=ICMNQFCH|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion|ENABLED=TRUE|PRIORITY=2|COMMENT= |DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=4mil¶

           

          Go back to CS and right mouse click in the rules tree and choose Import Rules.  Select the Solder Mask Expansion rule type and press OK. Navigate and select the file you just edited and press Open.  When it asks to clear existing rules prior to import is may be safest to click No.

           

          You should see the scope of the rule change now to IsVia.

          Click Apply and then OK to close the Rules editor.

           

          If you view the PCB in 3D you should see the vias now have solder mask encroached with a negative expansion.

           

          If you need to, you should be able to put a large negative value in the via expansion rule to fully tent.

           

          Good luck.