I hope someone can help me figure out why the FSBL is successful only after the board has been running for a while.
I am developing on the UltrazedEG board and it's carrier (IOCC) -> http://zedboard.org/product/ultrazed-EG. It has a Zync Ultrascale+ XCZU3EG-SFVA625.
My goal is to test the DDR, so I can't use it as program memory.The program has to run from the SD card, so I can't use the OCM either, since it is reserved by the bootloader.
I have modified the out-of the box setup by adding a 256KB BRAM at address 0x8000_0000 in vivado 2018.3 (plus a few other irrelevant changes)
In Xilinx SDK 2018.3 I have created 4 projects,
- The Hardware Platform Specification (importing the .HDF file from Vivado after generating Bitstream)
- The Board Support Package
- The FSBL based on the template
- One Hello World program (to keep this question simple, will be replaced with DDR testing code)
For the FSBL project, I have modified the compiler Symbols according to https://www.xilinx.com/support/answers/69754.html
And I have modified the bsp's page table (MMUTableL2) accordingly (fsbl_bsp>psu_cortexa53_0>libsrc>standalone_v6.8>src>translation_table.S)
.rept 0x0200 /* 0x8000_0000 - 0xBFFF_FFFF */
.8byte SECT + Memory /* 1GB lower PL changed Device -> Memory */
.set SECT, SECT+0x200000 .endr
I have also enabled more verbose debug messages from the FSBL in xfsbl_config.h
#define FSBL_DEBUG_DETAILED_VAL (1U)
I have modified the linker script for the Hello world program to generate two .elf files, one targeted to the DDR, one targeted to BRAM. I then use the bootgen GUI in the SDK (select Hello World project > Xilinx > Create Boot Image) to generate two .bin files that can be loaded on the SD card, for comparison.
When loading to the DDR, it works every time, when loading to the BRAM it has a weird behavior:
- If the board has been off for more than ~2 minutes, it fails. A subsequent boot quickly after will fail too.
- If the board has been on for more than ~30 seconds, it succeeds. Subsequent boots succeed too, until the board is left off for a while.
Deeper investigation shows me that the FSBL hangs at the very first access attempt to the BRAM done by f_read() function called by Xfsbl_SdCopy() in xfsbl_sd.c
I have tried many changes to the FSBL like adding a delay after the Bitstream is loaded (even a 40s delay!), adding extra check that the PL is ready, etc... but nothing I did changed the behavior described above.
I have attached a copy of the FSBL debug messages as well.
If you have any idea of what's going on, please tell me, I have exhausted ideas on my end.
[This question was initially posted on Xilinx's forums, but marked as SPAM]
aj_FSBL.txt.zip 879 bytes