I am currently trying to build a kernel module, which contains functions like cache-flushing.
Some background Information as to how my System is generated:
I am using the Xilinx-V2019.1-Toolchain (Vivado & SDK, PetaLinux Tools) to generate all the required Embedded Linux components like bootloader, kernel image and device tree. Furthermore I have cloned the Xilinx-Linux-Repository, switched to the V2019.1 branch and configured PetaLinux Tools to use the specific Xilinx-Linux-Repo to generate the components using the repository. My platform is the Avnet-UltraZed-EG-IOCC Board and I am using a Debian-10 root filesystem for development. The Module I am trying to compile has worked on other Zynq-7000 Dev. Boards which have a different CPU-Architecture (32-Bit).
The module won't compile, because I am trying to use kernel functions form a header which doesn't exist (outercache.h).
Regarding the outercache.h header, someone pointed out to me that this library can only be used on ARM-32-Bit-CPUs. As of right now I have worked through the arch/arm/include/asm/*.h and arch/arm64/include/asm/*.h within the Xilinx-Linux-Repository and found some other headers. But the problem persists, that the relevant headers (for example from the arm64-dir: cache.h, cacheflush.h) are not build. I have tried building the headers using PetaLinux Tools, as well as Cross Compiling using make xilinx_zynqmp_defconfig, make deb-pkg, make headers_install. Using the find command I have not figured out how to generate these cache headers, which could be the solution to my problem.
Another tip which I received on the Xilinx Forum was to include the following line CONFIG_OUTER_CACHE=y in the xilinx_zynqmp_defconfig, which seemed promising but also didn't help me generating the required headers.
The only cache-relevant header being built on my system is located under /usr/include/linux/bcache.h, but doesn't contain any helpful functions for my module.
So as of right now I am really desperate to find out, how the cache can be flushed on 64-Bit Architectures from the Xilinx Zynq UltraScale+ Series. Hopefully someone can help me out with this issue, it might also help future developers.
I am depending on this to work for my application which is why I am trying to get help from both Forums here as well as the Xilinx Forum (see https://forums.xilinx.com/t5/Embedded-Linux/Cacheflush-not-working/m-p/1009218#M35867)
I would appreciate all the help I can get and please reply should you need more details, screenshots or other information,
Message was edited by: Bjørn Hövding