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There are three modes of PCIe clocking. The FPGA can recover the clock from the data. The transceivers do not have to receive THAT specific clock, but do need a clock. If you are going to use this as an endpoint, you will need to convert the signaling somehow. The board has been setup as a root.
You can take a look at the UltraZed-EG, which also has a PCIe endpoint capable Carrier Card.
I saw it could only be used as root port. I now have an EG with carrier card, configured as endpoint.
I am having a difficult time writing to memory space - I always receive a Master Abort, although I can read and write configuration space. I have the card in a Windows PC and am using a utility to create read and write transactions.
Do you know of someone I can talk to to assist me? I have implemented the Xilinx answer 72076, https://www.xilinx.com/support/answers/72076.html but it is not funcitonal as an endpoint yet.
Is there a functional example that Avnet can provide for the UltraZed-EG on PCIe carrier card as an endpoint?
I'm sorry that we do not have such a public design. Do you know who your local FAE is? They can get in contact with our specialists and I think they might have something that can help related to this.
Does anyone have informationexperience regarding PCIe on the UltraZed EV SOM using the Carrier Card? Like to carrier card: UltraZed-EV Carrier Card | Zedboard
The documentation mentions that it includes a PCIe Root Port slot and does not mention the slot/device as an Endpoint.
It appears the PCIe clock is sourced from the carrier card and the pins on the slot connector for the clock lines do not connect to the FPGA at all. I think this prohibits use of the card as an Endpoint.
Are my assuptions correct? If so, is there an UltraZed combo that can perform as a PCIe endpoint? The Ultrazed EG SOM and the PCIe carrier card specifically mentions it as an Endpoint. Has anyone implemented this?
Thank you for any help you may provide.