7 Replies Latest reply on Oct 11, 2019 10:22 AM by jafoste4

    UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board

    andyy

      Hi @all,

       

      we have here an AES-ZU-PCIECC-G with AES-ZU3EG-1-SOM-I-G and AES-FMC-NETW1-G Rev1.0.

       

      Actually I need to run the both additional ethernet phys on Linux as eth interface.

       

      For that I used the project from here:

       

      http://zedboard.org/support/design/17956/141

      FMC_Network_lwIP_2018.2

      http://zedboard.org/sites/default/files/design/FMC-Network_lwip_V1.zip

       

      My questions:

       

      * The included constraint file: UltraZed_EG_PCIe_CC_Network.xdc is completly different to that constraint file on the product page: https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-fmc-netw1-g-3074457345635205181/ --> https://www.avnet.com/opasdata/d120001/medias/common/189/AES-FMC-NETW1-G-XDC-File.xdc Is someone able to tell me if this is correctly? If I did a test with the bare metal application of the tutorial, both phys are answering/responding.

      * Now I have the hdf file from the Vivado project and I like to build the device tree with the Xilinx SDK. I can see that GEM0 and GEM1 are connected to MIO's. So now the problem is that in the pcw.dtsi is a reference to @phy1 which is not existing:

       

      &gem0 {
          phy-handle = <&phy1>;
          phy-mode = "gmii";
          status = "okay";
          xlnx,ptp-enet-clock = <0x0>;
          psu_ethernet_0_mdio: mdio {
              #address-cells = <1>;
              #size-cells = <0>;
              gmii_to_rgmii_0: gmii_to_rgmii_0@8 {
                  compatible = "xlnx,gmii-to-rgmii-1.0";
                  phy-handle = <&phy1>;
                  reg = <8>;
              };
          };
      };
      &gem1 {
          phy-handle = <&phy1>;
          phy-mode = "gmii";
          status = "okay";
          xlnx,ptp-enet-clock = <0x0>;
          psu_ethernet_1_mdio: mdio {
              #address-cells = <1>;
              #size-cells = <0>;
              gmii_to_rgmii_1: gmii_to_rgmii_1@8 {
                  compatible = "xlnx,gmii-to-rgmii-1.0";
                  phy-handle = <&phy1>;
                  reg = <8>;
              };
          };
      };
      

       

      Which means i can't build the dtb file.

       

      --> Is there a patch or additional dtsi file available for the AES-FMC-NETW1 board that I can include for building the device tree?

      --> If not, how can I manually add @phy1 to the device tree?

       

      Best Regards

      Andy

        • Re: UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board
          jafoste4

          Hi Andy,

           

          When using the Network FMC with the UltraZed 3EG +PCIe Carrier Card you should be using the AES-FMC-NETW1-G-XDC-File.xdc.

           

          Here is a reference BSP we made way back when https://avtinc.sharepoint.com/:f:/t/ET-Downloads/EpcNLFg6YuhAv04zj2ZQJKABNslzmCDnatpghaXkvY68mQ  I would suggest you take a look at this to kick start your Linux Development.

           

          -Josh

            • Re: UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board
              andyy

              Hi Josh, thanks for the comment. The original constraint file is not working with this project. So this tutorial is described for the AES-FMC-NETW1 board. It is a mess to deal with different files... If this is the reason it is a shame. So actually I guess I need a patch for the U-Boot/Kernel compiling only to make @phy1 to work with. How did you go one in this matter?

                • Re: UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board
                  jafoste4

                  Hi Andy,

                   

                  In the BSP I just provided, we implemented the Network FMC using AXI_Ethernet. So the PL design is quite different than the lwIP design your currently using.

                   

                  Here is the system-user.dtsi file thats buried within that BSP.

                   

                  -Josh

                   

                   

                  /include/ "system-conf.dtsi"

                  / {

                  };

                   

                   

                  &gem3 {

                  status = "okay";

                  local-mac-address = [00 0a 35 00 02 90];

                  phy-mode = "rgmii-id";

                  phy-handle = <&phy0>;

                  phy0: phy@9 {

                  reg = <0x9>;

                  ti,rx-internal-delay = <0x5>;

                  ti,tx-internal-delay = <0x5>;

                  ti,fifo-depth = <0x1>;

                  };

                  };

                   

                   

                  &i2c1 {

                  status = "okay";

                  clock-frequency = <400000>;

                   

                   

                  i2cswitch@70 { /* U7 on UZ3EG SOM */

                  compatible = "nxp,pca9542";

                  #address-cells = <1>;

                  #size-cells = <0>;

                  reg = <0x70>;

                  i2c@0 { /* i2c mw 70 0 1 */

                  #address-cells = <1>;

                  #size-cells = <0>;

                  reg = <0>;

                  /* IIC_EEPROM */

                  eeprom@52 { /* U5 on UZ3EG IO Carrier*/

                  compatible = "at,24c08";

                  reg = <0x52>;

                  };

                  };

                  };

                  };

                   

                   

                  &qspi {

                  #address-cells = <1>;

                  #size-cells = <0>;

                  status = "okay";

                  flash0: flash@0 {

                  compatible = "micron,n25q256a"; /* 32MB */

                  #address-cells = <1>;

                  #size-cells = <1>;

                  reg = <0x0>;

                  spi-tx-bus-width = <1>;

                  spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */

                  spi-max-frequency = <108000000>; /* Based on DC1 spec */

                  partition@qspi-boot {

                  label = "qspi-boot";

                  reg = <0x0 0x780000>;

                  };

                  partition@qspi-bootenv {

                  label = "qspi-bootenv";

                  reg = <0x780000 0x80000>;

                  };

                  partition@qspi-linux {

                  label = "qspi-linux";

                  reg = <0x800000 0x3800000>;

                  };

                  };

                  };

                   

                   

                  /* SD0 eMMC, 8-bit wide data bus */

                  &sdhci0 {

                  status = "okay";

                  bus-width = <8>;

                  max-frequency = <50000000>;

                  };

                   

                   

                  /* SD1 with level shifter */

                  &sdhci1 {

                  status = "okay";

                  max-frequency = <50000000>;

                  no-1-8-v; /* for 1.0 silicon */

                  };

                   

                   

                  /* ULPI SMSC USB3320 */

                  &usb0 {

                  status = "okay";

                  };

                   

                   

                  &dwc3_0 {

                  status = "okay";

                  dr_mode = "host";

                  phy-names = "usb3-phy";

                  };

                   

                   

                  &spi0 {

                          status = "okay";

                          spidev0: tpm_spi_tis@0{

                                  compatible = "tcg,tpm_tis-spi";

                                  reg = <0>;

                                  spi-max-frequency = <250000>;

                          };

                  };

                   

                   

                  &axi_ethernet_0 {

                  phy-mode = "rgmii-id";

                  xlx,ptp-enet-clock = <0x0>;

                  local-mac-address = [00 0a 35 00 01 23];

                  phy-handle = <&axieth0_phy>; 

                   

                   

                  mdio { 

                  #address-cells = <1>; 

                  #size-cells = <0>; 

                  axieth0_phy: phy@1 {

                  reg = <1>;

                   

                   

                                          /* Delays are relative to the observation made from the PHY */

                  /* Delay values can be made with increments of 60ps for KSZ9031RNX PHY. */

                  rxc-skew-ps = <1860>; /* Skew control of RX_CLK pad output */

                  txc-skew-ps = <900>; /* Skew control of GTX_CLK pad input */

                  txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */

                  rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */

                  rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */

                  rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */

                  rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */

                  rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */

                  txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */

                  txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */

                  txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */

                  txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */

                  };

                  };

                  };

                   

                   

                  &axi_ethernet_1 {

                  phy-mode = "rgmii-id";

                  xlx,ptp-enet-clock = <0x0>;

                  local-mac-address = [00 0a 35 00 01 24];

                  phy-handle = <&axieth1_phy>;

                   

                   

                  mdio { 

                  #address-cells = <1>; 

                  #size-cells = <0>; 

                  axieth1_phy: phy@1 {

                  reg = <1>;

                   

                   

                                          /* Delays are relative to the observation made from the PHY */

                  /* Delay values can be made with increments of 60ps for KSZ9031RNX PHY. */

                  rxc-skew-ps = <1860>; /* Skew control of RX_CLK pad output */

                  txc-skew-ps = <900>; /* Skew control of GTX_CLK pad input */

                  txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */

                  rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */

                  rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */

                  rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */

                  rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */

                  rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */

                  txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */

                  txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */

                  txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */

                  txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */

                  };

                  };

                  };

                  1 of 1 people found this helpful
                    • Re: UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board
                      andyy

                      Hi Josh, thanks again for the replay. Is there a possibility to get a small Vivado project with the AXI implementation? I'm normally not doing Vivado projects at all. But in this case I guess, I have no chance...

                        • Re: UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board
                          jafoste4

                          Hi Andy,

                           

                          If you unzip the bsp i sent you it will contain the hardware project we used in this build.

                          (Unzip it twice and then go the  following directory uz3eg_pciec_ccd_2017_4~\uz3eg_pciec_ccd_2017_4\hardware\UZ3EG_PCIEC)

                           

                           

                          -Josh

                            • Re: UltraZed and support for the AES-FMC-NETW1-G Rev1.0 board
                              andyy

                              Hi Josh, now I extracted the file and used your uz3eg_pciec_ccd_hw.hdf file for building my SDK workspace which I'm using at version 2018.2 of the Xilinx SDK. FSBL and PMUFW is working. But there is a problem during the generation of the device tree. If I'm creating a device tree project I got an error:

                               

                               

                              09:48:31 ERROR    : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_axi_ethernet::generate : invalid command name "::hsi::utils::get_other_intf_pin"
                                  while executing
                              "::hsi::utils::get_other_intf_pin $intf_net $intf"
                                  (procedure "::sw_axi_ethernet::generate" line 61)
                                  invoked from within
                              "::sw_axi_ethernet::generate axi_ethernet_0"
                              
                              09:48:31 ERROR    : (XSDB Server)ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
                              
                              09:48:31 ERROR    : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp.
                              
                              09:48:31 ERROR    : Error generating bsp sources: Failed in generating sources
                              09:48:31 ERROR    : Failed to regenerate sources for BSP project device_tree_bsp_0
                              org.eclipse.core.runtime.CoreException: Internal error occurred while generating bsp sources. Please check the SDK Log view for further details.
                                  at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.internalGenerateBsp(RegenBspSourcesHandler.java:178)
                                  at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.access$2(RegenBspSourcesHandler.java:163)
                                  at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler$1$1.run(RegenBspSourcesHandler.java:131)
                                  at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2240)
                                  at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2267)
                                  at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler$1.run(RegenBspSourcesHandler.java:135)
                                  at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:119)
                              

                               

                              Do I need to use the SDK which you previously used?