Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Mar 26, 2020 11:23 AM
Mar 26, 2020 11:23 AM
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
I would appreciate any comments on a process on how to make the DDR3 SDRAM MIG work without using the AXI interface in VHDL. As a target platform I have the Digilent Arty S7 board.
I tried this during my Roadtest of the Arty S7 but was not successfull and really like to revisite this.
Thanks,
- W.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
What do you mean without using VHDL? Have you tried dragging and dropping the DDR memory block from the boards element of the properties onto the block diagram?
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Sorry, my typing is unclear. I meant: not using the AXI as interface, and using VHDL as my language of choice.
I have never used block diagrams and graphical input in Vivado and intend to keep it that way.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Looking at the block diagram for the Zynq-7000 SoC, the Memory Interfaces, including the DDR3, is connected to the PL via a AXI 32-bit, so it would be interesting if this is directly accessible without going through the AXI.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
My board is the Arty-S7. It has 'only' a Spartan7 FPGA not a Zync SoC. So I need an IP core to connect to the DDR3.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
5 of 5 people found this helpfulThe arty S7 has a MIG file with it which will set up for the DDR3 on the board. However the easiest way to generate this is to use the IP integrator flow and drag and drop the DDR from the external memory on to a block diagram. This will configure the MIG for the Arty DDR.
However, I know you want to work with VHDL flow, so once you have done this I would then generate a VHDL / Verilog wrapper and just include that wrapper in your VHDL file.
To do this make all the IO external - by selecting the MIG and right clicking and saying make external
Then you can create a VHDL / Verilog Wrapper - you should be able to use this in your VHDL design
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Thanks, that is an interesting approach and I will try that out.
I also learnt, that Digilent Arty-S7 board comes with a demo design that uses the DDR3 memory. It was recommended to start with the demo code and add my functionality instead of starting from scratch. I have not found the code yet, but it might be a 2nd option to get to a working code base.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Awesome! It's great that adamtaylorcengfiet is a resource on element14 for Programmable SoC questions. I'm sure I will have many as I finish my Digilent Zybo Z7 RoadTest. I do find Adam's Microzed Chronicles quite useful though.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Really glad you find them useful
Thanks for reading them
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
I didn't want to clog up this thread with general comments other than questions, but I have to agree with jomoenginer - it's great that adamtaylorcengfiet is here on E14 to help. The MicroZed Chronicles are an amazing source of information and inspiration on all things Zynq.
When I have a question that isn't totally dumb, I'll be sure to ask!
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
I wonder if somebody did already make a PCIe driver for the AxiEthernet via the XDMA?
I feel so lost.
It's incredbliy hard to get it right as of the interrupts and that it loses the completed count e.g sometimes i get a race between driver and fpga.
We got the TX Path working but the RX seems to just not care about any packet arriving…
We are using the arty 7.
But maybe this is the wrong place to ask…
(Can't get a FAE sadly as the contact was lost.) -
Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
1 of 1 people found this helpfulFor what it's worth, there is an Integrating Arm Cortex-M soft CPU IP into FPGAs virtual workshop that features Adam Taylor as an instructor and uses the Digilent Arty S7-50T to be held August 14th, 2019.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
1 of 1 people found this helpfulA couple of areas I'm interested in exploring with FPGA ( initially using the TUL PYNQ-Z2 board ) are:
1) HDMI video capture and processing where the PYNQ-Z2 is used for low cost HDMI capture / pass through for basic object/pedestrian detection/tracking which is then further used for indexing video recordings or automated tracking such as remote camera control.
(It would also be interesting to look at accessing the HDMI I2C bus to extract/inject EDID information via the PYNQ framework to enable video signal diagnostic type applications.)Some interesting online resources I've found in this area so far are:
- Adam Taylor - Use Python, Zynq and OpenCV to Implement Computer Vision
https://www.hackster.io/adam-taylor/use-python-zynq-and-opencv-to-implement-computer-vision-361e1b
which is based on the Arty Z7-20 so I am expecting similar performance on the PYNQ-Z2. THe 29.7fps reported looks good
enough for experimentation purposes with an option to move up to the UltraScale+ boards.
- Adrian Rosebrook - Pedestrian Detection OpenCV
https://www.pyimagesearch.com/2015/11/09/pedestrian-detection-opencv/
using OpenCV's histogram of gradients model for pedestrian detection.
- Adam Geitgey - snagging parking spaces with mask r-cnn and python
https://medium.com/@ageitgey/snagging-parking-spaces-with-mask-r-cnn-and-python-955f2231c400
Computer vision with some machine learning applied.
Some inital questions perhaps arise around what are the quick wins in terms of hardware acceleration vs productivity in this area. A lot of the processing appears to still be done in software on the ARM processor as oppossed to being accelerated on the FPGA. Are there perhaps more appropriate computer vision libraries that would make better use of the FPGA hardware ?
2) Serial data capture and processing where the FPGA hardware or MicroBlaze subsystem are used to create a customizable UART to decode the incoming serial data and make it available via the PYNQ framework. Perhaps using the hardware to detect
certain conditions to filter the data stream off-loading some of the processing.
One application I had in mind was to be able to ingest a DMX512 lighting protocol on a RS-485 interface and have Python scripts react when certain data frames are sent out from a lighting console. Perhaps using the HDMI inputs and outputs to pass through live video and switch it with still images (or computer generated art / real time data from the web) controlled by the lighting console to create intelligent lighting displays using video projection or video walls.For experimentation purposes one perhaps could even use the MicroBlaze subsystem to set up a virtual DMX512 transmitter and and virtual DMX512 receiver and access both via the PYNQ framework all on the one board without any worries of timing issues.
However at a more general level, similar approaches perhaps could be used for more general serial data acquisition and status display on an attached HDMI screen as a protocol diagnostic tool.
Unfortunately there doesn't yet appear to be PYNQ driver available for the existing PMOD 485 interface
https://store.digilentinc.com/pmod-rs485-high-speed-isolated-communication/
and I've not found much in the way of associated on-line FPGA tutorials in this particular area, especially not with using the PYNQ framework.-
Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
2 of 2 people found this helpfulThe Pynq Z2 should give a similar performance if you use the OpenCV overlay as outlined in the blog of mine you mention. If you want to look at the Ultra96 which is the best board available for many projects I think in my opinion then you can get significant speeds up including >100 frames per second for optical flow algorithm implementation https://blog.hackster.io/microzed-chronicles-ultra96-and-pynq-da3b22cc982
Regarding the PYNQ driver for the Pmod485 it is possible to write C code for the micro-blaze in the Jupyter note book, so you could use this approach and leverage the Pmod485 driver from the Digilent PMod library. I covered it briefly in a blog here https://blog.hackster.io/pynq-edition-interfacing-with-pmods-arduino-and-raspberry-pi-61676f9f0fab
- Adam Taylor - Use Python, Zynq and OpenCV to Implement Computer Vision
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
- What trends do you see happening in the FPGA world in the upcoming years?
- Do you see FPGAs moving into the realm of PC's? GPUs, even though they are completely different, have gained a lot of attention in the general computation arena, while at the same time FPGAs haven't apparently gained much more popularity. What do think is the cause of this?
- Do you see any upcoming official opening of the bitstream formats? The formats appear to be slowly being reverse-engineered, whats is the rationale in keeping them closed? I would think that opening them would allow the creation of an ecosystem of 3rd party tools which probably would attract more users to the platform. Making software opensource could also lower development costs, etc. What are your thoughts on all this?
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
2 of 2 people found this helpfulThese are great questions.
I think the trend is pretty clear they are evolving (and have been for many years) in to platforms, which combine different compute engines e.g Programmable Logic and Processors cores. The Xilinx Versal devices take this to the next step. These heterogeneous devices enable the deployment of elements of the application being developed to the most optimal compute engine, what we will see along with rapid device development in this area is a significant increases in development SW which offers a combined platform which can be used to develop the application and then deploy elements as required in the different engines example include SDSoC, SDAccel for example.
I am not sure PC's will ever contain a programmable logic device on board the motherboard but I think programmable logic will be easily available via the cloud e.g. AWS and using modules like the Alveo card either locally or in the cloud. GPU's became popular for computation as PC do need them as well for graphics in a number of applications therefore it was a natural extension to be able to use them for computation as needed.
I do not and I am not sure why people get hung up on it in my opinion. I am not 100% sure why they are kept closed behind the need for IP protection and most importantly getting the bitstream wrong could potentially damage the device which will cause several issues. If it was me I would focus open tool development on areas such as simulation, verification, synthesis, formal verification etc I know there is work going on in this area. Regarding development costs, most vendors offer free versions which cover a significant range of components, which should address the most maker, hobbyist and many commercial applications. While the larger projects using tools which require licensing are often developed by organisations which can afford the costs. I have also found the vendors very willing to talk and support if your doing interesting projects.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
1 of 1 people found this helpfuladamtaylorcengfiet wrote:
I am not sure PC's will ever contain a programmable logic device on board the motherboard but I think programmable logic will be easily available via the cloud e.g. AWS and using modules like the Alveo card either locally or in the cloud. GPU's became popular for computation as PC do need them as well for graphics in a number of applications therefore it was a natural extension to be able to use them for computation as needed.
Actually, FPGAs have been placed on Motherboards for some time now,.
Intel is now producing Xeon processors that include a FPGA in the same package as well as offering the Intel Acceleration Stack for Intel Xeon® CPU with FPGAs. However, as you mentioned, these would be more inline with the Web Giants and such due to the cost of the devices at this time.
I like the comment regarding open source tools. This is starting to be a thing now where folks are getting frustrated with the FPGA vendor tools and are reverse engineering the FPGA code to create their own open source tools to program the device. I suspect this will continue to expand.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
2 of 2 people found this helpfulI knew FPGA where on motherboards but as I understand it, it is not accessible by the user for programming instead it is smallish device which provides functions on the motherboard design. I read the question as being will FPGA be deployed on motherboards in a manner that they are accessible by the user to program and accelerate algorithms like you can with GPU's
It will be interesting to see what the open source community does, I suspect your right re reverse engineering.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
John Beetem
Aug 3, 2019 9:05 AM
1 of 1 people found this helpfulneuromodulator wrote:
- Do you see any upcoming official opening of the bitstream formats? The formats appear to be slowly being reverse-engineered, whats is the rationale in keeping them closed? I would think that opening them would allow the creation of an ecosystem of 3rd party tools which probably would attract more users to the platform. Making software opensource could also lower development costs, etc. What are your thoughts on all this?I've been advocating for open bitstream formats for decades. It's great that some are being reverse-engineered and I heartily congratulate the developers of IceStorm and related tools.
I don't see FPGA vendors opening and documenting their bitstream formats. They have various "official" reasons, none of which I find credible. I've written about this a lot over the years at element14, for example in my article Taming the Wild Bitstream. Here's an excerpt:
The excuse most commonly heard from FPGA vendors is that they insist their customers want the bitstream format to be secret to prevent reverse-engineering customer designs. OK, that makes sense except for one thing: millions of μP/μC-based products are designed and sold each year using open CPU architectures, yet there is very little worry that someone is going to reverse-engineer those designs. IMO most FPGA designers would gladly have better tools in exchange for open bitstream formats.
Most FPGAs are part of hardware/software systems, and unless the FPGA performs a trivial function, trying to understand what it does and how it interacts with the software is pretty nasty. Indeed, it’s hard enough to understand someone else’s FPGA even if you have commented VHDL/Verilog source code :-) The best you can do is to make an exact copy, which you can do now with the bitstream itself. Yet people rarely do, because you’re much better off designing better products with better features than copying your competitor’s last-generation products and trying to modify them enough so that you’re not blatently violating copyright.
I also make the claim in my article that closed bitstreams have held back FPGAs since their inception and have prevented FPGAs from having the huge success of microprocessors and microcontrollers. Where would microprocessors be today if Intel had kept its instruction set secret and insisted that everyone program in PL/M?
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Is there an ADC in the Ultra 96 board and if so how do I access it using pynq?
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
1 of 1 people found this helpfulThere is a XADC available, though I am not sure what the pins are mapped to externally you would have to check the schematics.
You can access the XADC using the IIC drivers check by blog here
https://blog.hackster.io/microzed-chronicles-petalinux-and-xadc-9ae052539d1f
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
ralphjy
Oct 23, 2019 7:41 AM
This question is for adamtaylorcengfiet -
I'm one of the trainees in the Path II Programmable course. I'm encountering an issue that hopefully you've seen before. At the end of HW Lab7 when I am trying to write the bitstream for the design with new IP added, synthesis runs successfully but implementation fails during optimization.
Here is an excerpt from the impl/runme.log:
Starting Logic Optimization Task
Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
ERROR: [IP_Flow 19-3805] Failed to generate and synthesize debug IPs.
ERROR: [Common 17-161] Invalid option value '0' specified for '-jobs'.
ERROR: [Chipscope 16-330] Synthesis of Debug Cores has failed
Phase 1 Generate And Synthesize Debug Cores | Checksum: 24bc6163a
Time (s): cpu = 00:01:01 ; elapsed = 00:03:50 . Memory (MB): peak = 2532.340 ; gain = 1.000 ; free physical = 1191 ; free virtual = 3762
INFO: [Common 17-83] Releasing license: Implementation
17 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
opt_design failed
ERROR: [Chipscope 16-338] Implementing debug Cores failed due to earlier errors
INFO: [Common 17-206] Exiting Vivado at Tue Oct 22 20:02:55 2019...
I can send you the full synth and impl logs if that will help. I saw on the Xilinx forum that this could be related to the version of Ubuntu installed. I wanted to check with you before I go through trying to install another version. Here is the link to the forum https://forums.xilinx.com/t5/Implementation/Invalid-option-value-0-specified-for-jobs/td-p/881190
I am running Ubuntu 16.04.6 in the VM.
I also tried running the tcl command "check_ip_cache -clear_output_repo"
Thanks,
Ralph
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
1 of 1 people found this helpfulHi Ralph
2018.3 I assume you are using that tool chain, does not support that version of Ubuntu it supports 16.04.03 or 16.04.04 which might be the cause of the issue
Adam
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
ralphjy
Oct 25, 2019 10:19 AM
Hi Adam,
Thanks. I had explicitly not upgraded to Ubuntu 18.04 and Xilinx 2019.1 because I did not want to have compatibility issues with the course. Is it better to upgrade now or should I try to revert back to 16.04.03?
Interestingly, I had continued to the next lab using the HDF solution that you provided and I did not have this issue generating the bitstream for the final lab. I guess my main concern is that I don't run into problems when I move on to my project after I finish the course. What specific tool flow would you recommend?
Ralph
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
The course I think is designed around 2018.3 so you should use that tool chain and make sure the VM aligns with it. That way you should be able to follow along with the labs nice and easily and not hit any issues re IP versions etc.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Hello,
I have a question with regards to the project Adam has posted under here:
https://www.hackster.io/adam-taylor/creating-an-fpga-based-low-cost-imaging-system-cb18af#comments
Rgearding the quote below:
As we have no VDMA it is important the video output on the AXIS stream is a contiguus block and that TValid does not assert and deassert during the active pixel period.
Can you use a AXIS clock crossing block instead of the FIFO or is that needed to avoid TVALID deserting periodically during the active pixel period?
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
No the FIFO is to buffer a pixel line so we do not get blank spots in the display when we are outputting the video
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
How do you deal with a scenario where the camera is operating on a different domain clock?
Wouldn't there be back-pressure (TVALID toggling) from the AXIS to Video out.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
The SDK (2019.1) under Ubuntu 18.04.3 will not complete loading, but halts silently when loading eclipse components. The host uses an INtel Core I7-3770 CPU with 16 GB or memory and has plenty of memory and disk available when I invoke the SDK from Vivado.
How can I find out what is causing the halt?
Thanks
Cliff
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
1 of 1 people found this helpfulYou could take a look in the SDK log, I think it will be the project directory <project>.sdk
However, the version of Linux your using does not look to supported in 2019.1 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug973-vivado-release-notes-install-license.pdf states 18.04.01
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
The SDK.log has informational messages only with no errors or warnings.
Hopefully I can get the OS downgraded to x.x.1 without a lot of trouble.
Thanks!
Cliff
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
It seem silly to me that an vendor such as Xilinx would pick nits over a minor version of an OS such as 18.04.1 vs 18.04.3 for Vivado.
Post any messages you see from the SDK log as Adam states and the error that you are seeing when Vivado runs. You might want to check the output of 'dmesg' and your '/var/log/syslog' for any errors as well.
However, you could install Virtualbox and create a Ubuntu 18.04.1 VM to run Vivado in without blowing away you running OS.
Again, this just seems silly. I personally run Vivado on CentOS 7.6 which is not listed as supported, but I got it to work non the less.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
I'm going to try installing version 2018.3 on Ubuntu 18.04.1, trying to minimize any issues with versions.
I noticed that the SDK installer mentions "Additional library installation required" for Ubuntu in the "Supported operating systems" panel, but I can't find any information on the required additional libraries. What additional libraries are needed and are they prerequisites for the installer or running the SDK?
Thanks
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
I'm going to post as an original item for visibility. Sorry for the duplication.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Hi Adam (adamtaylorcengfiet ),
I am one of the trainees for the Path II Programmable training program. I am working on the PetaLinux Lab 1. When I configured the Kernel using petalinux-config tool, the configuration went fine. However, when exited from the configuration tool, it showed three lines of error messages (highlighted below). After trying to run petalinux-build tool, it gave two lines of error messages (highlighted below). Can you tell me why it caused the error and how to solve it? Thanks.
$petalinux-config --get-hw-description=../
INFO: Getting hardware description...
INFO: Rename design_1_wrapper.hdf to system.hdf
[INFO] generating Kconfig for project
[INFO] menuconfig project
configuration written to /media/sf_shared/Xilinx/petalinux/2018_3/support_documents/v2/lab1_example/project-spec/configs/config
*** End of the configuration.
*** Execute 'make' to start the build or try 'make help'.
[INFO] sourcing bitbake
ERROR: Failed to source bitbake
ERROR: Failed to config project.
ERROR: Get hw description Failed!.
$ petalinux-build
[INFO] building project
[INFO] sourcing bitbake
ERROR: Failed to source bitbake
ERROR: Failed to build project
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
I checked the log files. The first problem I noticed is that my default Python version is 3.x not 2.x required by PetaLinux tools. I fixed the problem but still failed the build. Here's the latest content of build.log:
[INFO] building project
[INFO] sourcing bitbake
SDK environment now set up; additionally you may now run devtool to perform development tasks.
Run devtool --help for further details.
You had no conf/local.conf file. This configuration file has therefore been
created for you with some default values. You may wish to edit it to, for
example, select a different MACHINE (target hardware). See conf/local.conf
for more information as common configuration options are commented.
You had no conf/bblayers.conf file. This configuration file has therefore been
created for you with some default values. To add additional metadata layers
into your configuration please add entries to conf/bblayers.conf.
The Yocto Project has extensive documentation about OE including a reference
manual which can be found at:
http://yoctoproject.org/documentation
For more information about OpenEmbedded see their website:
INFO: Adding user layer: /media/sf_shared/Xilinx/petalinux/2018_3/support_documents/v2/lab1_example/project-spec/meta-user
NOTE: Starting bitbake server...
NOTE: Retrying server connection... (Traceback (most recent call last):
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py", line 441, in setup_bitbake
server = bb.server.process.BitBakeServer(lock, sockname, configuration, featureset)
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/server/process.py", line 385, in __init__
self.sock.bind(os.path.basename(sockname))
PermissionError: [Errno 1] Operation not permitted
)
WARNING: /tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py:476: ResourceWarning: unclosed <socket.socket fd=7, family=AddressFamily.AF_UNIX, type=SocketKind.SOCK_STREAM, proto=0>
logger.info("Retrying server connection... (%s)" % traceback.format_exc())
WARNING: /tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py:430: ResourceWarning: unclosed file <_io.TextIOWrapper name='/media/sf_shared/Xilinx/petalinux/2018_3/support_documents/v2/lab1_example/build/bitbake.lock' mode='a+' encoding='UTF-8'>
topdir, lock = lockBitbake()
NOTE: Reconnecting to bitbake server...
Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection...
NOTE: Starting bitbake server...
NOTE: Retrying server connection... (Traceback (most recent call last):
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py", line 441, in setup_bitbake
server = bb.server.process.BitBakeServer(lock, sockname, configuration, featureset)
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/server/process.py", line 385, in __init__
self.sock.bind(os.path.basename(sockname))
PermissionError: [Errno 1] Operation not permitted
)
WARNING: /tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py:476: ResourceWarning: unclosed <socket.socket fd=9, family=AddressFamily.AF_UNIX, type=SocketKind.SOCK_STREAM, proto=0>
logger.info("Retrying server connection... (%s)" % traceback.format_exc())
NOTE: Reconnecting to bitbake server...
Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection...
NOTE: Starting bitbake server...
NOTE: Retrying server connection... (Traceback (most recent call last):
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py", line 441, in setup_bitbake
server = bb.server.process.BitBakeServer(lock, sockname, configuration, featureset)
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/server/process.py", line 385, in __init__
self.sock.bind(os.path.basename(sockname))
PermissionError: [Errno 1] Operation not permitted
)
WARNING: /tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py:476: ResourceWarning: unclosed <socket.socket fd=11, family=AddressFamily.AF_UNIX, type=SocketKind.SOCK_STREAM, proto=0>
logger.info("Retrying server connection... (%s)" % traceback.format_exc())
NOTE: Reconnecting to bitbake server...
Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection...
NOTE: Starting bitbake server...
NOTE: Retrying server connection... (Traceback (most recent call last):
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py", line 441, in setup_bitbake
server = bb.server.process.BitBakeServer(lock, sockname, configuration, featureset)
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/server/process.py", line 385, in __init__
self.sock.bind(os.path.basename(sockname))
PermissionError: [Errno 1] Operation not permitted
)
WARNING: /tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py:476: ResourceWarning: unclosed <socket.socket fd=13, family=AddressFamily.AF_UNIX, type=SocketKind.SOCK_STREAM, proto=0>
logger.info("Retrying server connection... (%s)" % traceback.format_exc())
NOTE: Reconnecting to bitbake server...
Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection...
ERROR: Unable to connect to bitbake server, or start one
NOTE: Retrying server connection... (Traceback (most recent call last):
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py", line 441, in setup_bitbake
server = bb.server.process.BitBakeServer(lock, sockname, configuration, featureset)
File "/tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/server/process.py", line 385, in __init__
self.sock.bind(os.path.basename(sockname))
PermissionError: [Errno 1] Operation not permitted
)
WARNING: /tools/petalinux-v2018.3-final/components/yocto/source/aarch64/layers/core/bitbake/lib/bb/main.py:476: ResourceWarning: unclosed <socket.socket fd=13, family=AddressFamily.AF_UNIX, type=SocketKind.SOCK_STREAM, proto=0>
logger.info("Retrying server connection... (%s)" % traceback.format_exc())
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection...
ERROR: Unable to connect to bitbake server, or start one
ERROR: Failed to add user layer: /media/sf_shared/Xilinx/petalinux/2018_3/support_documents/v2/lab1_example/project-spec/meta-user
ERROR: Failed to source bitbake
ERROR: Failed to build project
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Found answer myself: https://forums.xilinx.com/t5/Embedded-Linux/petalinux-build-fails-in-VirtualBox-shared-folder/td-p/875986
Basically, creating PetaLinux project in VM shared folder doesn't work. I have to use VM local folder.
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
ralphjy
Nov 5, 2019 3:49 PM
Hi Adam (adamtaylorcengfiet ),
I'm working on completing the 4th week of the Path II Programmable training and I'm looking ahead to the project that I'm going to try doing. I saw that Xilinx had created a demo that is very similar to what I would like to implement and wondered if you would have some insight as to how it was partitioned between PS and PL. Here is the link to the announcement: https://forums.xilinx.com/t5/AI-and-Machine-Learning-Blog/New-AI-Edge-Demos-available/ba-p/965399 . I'd like to process RTSP video streams from IP cameras and possibly an NVR and do some detection and response. You've done a lot of video processing examples and I was hoping that you could give me some pointers to relevant examples. The streams would be H264 encoded.
Thanks,
Ralph
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Duplicate Post - the original might have been lost in the chain.
I'm going to try installing version 2018.3 on Ubuntu 18.04.1, trying to minimize any issues with versions.
I noticed that the SDK installer mentions "Additional library installation required" for Ubuntu in the "Supported operating systems" panel, but I can't find any information on the required additional libraries. What additional libraries are needed and are they prerequisites for the installer or running the SDK?
Thanks
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Re: Get Your Xilinx FPGA/Programmable SoC Questions Answered here
Adam,
I have a couple of questions for using the MIG DDR3 interface for a Arty S7-50.
- How to configure the clk_ref_i and sys_clk_i for the DDR3 MIG?
- There are two clocks on the board 12Mhz sys_clk and 100Mhz ddr_clock
- Why would there be two clocks on the board?
- Use the clocking wizard and use ddr_clk 100Mhz and generate two clocks 100Mhz for sys_clk_i and 200Mhz for the sys_ref_i clock into the MIG?
- Can the ddr_clk be connected into the MIG without using the clock wizard?
- Once the MIG is created, should the MIG clock be used for the system? i.e. MicroBlaze, UART, etc?
- Is there an advantage to using the MIG generated clock for the design?
- Is it better to use the 100Mhz clock created from the clock wizard?
- How to configure the clk_ref_i and sys_clk_i for the DDR3 MIG?
