5 Replies Latest reply on May 18, 2020 9:11 AM by harahika

    Basic bare metal hardware design and software application missing for U96v2

    harahika

      Hello,

      I have been using Xilinx tools (Vivado 2018-2019.1, SDK, Petalinux tools)  for previous Zynq7000 projects but in my current project we are using Zynq Ultrascale+ MPSoC.
      We bought an Ultra96v2 dev board to test the chip that's going on the prototype pcb.  I can run the out-of-box instructions on the card for Linux platform and can even get PYNQ to work.

      My problem is that our application isn't targeting Linux at this point. It is a hard real-time control application and runs on the R5-core.
      We are NOT interested in machine vision or any of that hype and running linux as master is not an option here.

      There doesn't seem to be any reference design or decent example of creating a basic hardware design with PS-block, some GPIOs, UART, Timers, non-volatile memory etc.
      I have found the board preset and constraints files from Github, but failed to create even a simple design in Vivado because just adding the Zynq PS-block and applying board presets induces weird errors that lead down a rabbit hole.

      Can somebody share a design, tutorial or something targeting Vivado and SDK (not Vitis) version 2019.1 and bare-metal/FreeRTOS development?
      I'm starting to feel really frustrated with the lack of simple examples. Moreover Vitis seems to break all backward compatibility and only target high-end devices, ML etc. so those examples are out of the question.

      Thanks,
      Harri