actually I try to debug a logic on my Ultra96 with the Xilinx ILA(Integrated Logic Analyzer) and I have issues that the logic won't be detected by the Hardware Manager after programming.
- I have created the project with the bdf template and configured the block diargram as followed
- Do the I/O Planning after synthesis
- Inserted the debug core by usage of the debug wizard
- Run implementation & Bitstream generation
- Open Hardware Manager & Program the device
After reading a lot in the internet about setting up the ILA and debug probes I get always the same issue in Vivado 2018.3:
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xczu3 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
Potential issues could be as Xilinx mentioned in other posts in the Xilinx Forum:
In the attachment you find the archived project for analysis.
Is there a issue with the PS-PL Clock setup? Can this clock be used for debugging with the ILA?
Is it possible to debug logic in the PL with the USB->JTAG adapter board "AES-ACC-U96-JTAG" from AVNET?
What other issues could block me to debug my very simple design?
When I got this problem fixed, I would like to provide a tutorial for the community.
HDL_Start_DebugProject_1.xpr.zip 14.0 MB