Why do you need to change the IOPLL divider?
You may want to examine the known-good clocking settings in the board definition (BDF) for the Ultra96-V2 board:
<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2" value="0"/> <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV" value="45"/> <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA" value="0"/> <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/> <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" value="0"/> <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" value="3"/>
I didn't want to change the IOPLL. Vivado 2019.2 complains that clock (with default settgins) are out of range.
It shows that IOPLL after multiplication is 1485MHz and it should be 1500MHz.
It looks like there is a problem within Vivado... but can't figure out what is it. Messages provided by Vivado are not helpful.
The same goes for "default part"... what part is it related with...? Can't guess...
It gets a bit frustrating if you are not able to fix something because you don't know what to fix.
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I forgot to mention in my previous reply that the blog post "Avnet HDL git HOWTO" may be helpful if you want to target the Ultra96-V2 board in Vivado and use the known-good PS configuration, clocking, etc. settings specified in the BDF file. You can use this to compare to your custom Vivado project.
Thank you! I'll take a look on it.
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I recently became aware of an issue that might be affecting you. Are you using native or VM Linux? If so, which version?
See this post by Javier Garcia: https://ohwr.org/project/soc-course/wikis/Custom-Board-Definition-Files . Note this key message:
The only presets that apply to the Ultra96-V2 are those in the zynq_ultra_ps_e_preset entry, but there is a critical problem with them as it produces different outcomes depending on your Linux distribution, e.g.:
If you use Vivado in Ubuntu 16.04.6, the design works.
If you use Vivado in Ubuntu 18.04.4, the design doesn't work.
I personally have been using Ubuntu 16.04, which may explain why I haven't seen your specific problem. I don't see that Javi published what the specific error is when 18.04.4 doesn't work, but it is related to the LPDDR4 so definitely worth a try.
We will be investigating further and updating the Avnet BDF to correct these issues.
Many thanks to Javi and GL Research for publishing this research!
I'm Arch Linux user and it is native installation.
Thanks for link to course on BDF, I appreciate it a lot.
Hm... referring to different outcome of the Vivado depending on the distribution or its version, shouldn't it be an issue?
I've downloaded recent version of Vivado and exactly the same project work well there, I mean it finished synthesis and produced output that can be used in further development.
I didn't change anything just used simples tutorial from AVNET for generating hardware layer for the board.
There were no complains about IOPLL and "Cannot identify default part." error either.
As I have already written, error messages are fuzzy and didn't provide much information about real cause of the problems...
Thanks for your support guys!
It is good to be here and have one to ask if problem occurs.
Regarding the various distribution versions, it shouldn't matter which one you use as long as it is supported by Xilinx. I think the Xilinx Support may be the key to understanding some of this. You can see the Supported OS in the Release Notes.
As you can see, Ubuntu 18.04.4 wasn't officially supported in 2019.2, which may explain why the BDF usage is different. I think there are still some issues identified with the BDF, so we will still address them.
Regarding Arch Linux, I do not see that on the official list for either 2019.2 or 2020.1, so you will want to exercise some caution there. Here is the 2020.1 list:
I'm new to Xilinx and Ultra96-v2 boards.
I've been trying to create hardware descripion in Vivado and went to error situation.
There is wrong IOPLL divider set.
When I change it to 91 (including enable of divider 2) then I have following error:
[BD 41-1273] Error running post_config_ip TCL procedure: unexpected "," outside function argument list
::xilinx.com_ip_zynq_ultra_ps_e_3.3::post_config_ip Line 47"
Besides that I see a number of: "[IP_Flow 19-2373] Cannot identify default part." errors.
Can you help me with those?