0 Replies Latest reply on Jul 29, 2020 9:33 AM by narrucmot

    AXI CDMA problem




      I added CDMA to my design to transfer data from DDR to BRAM. I exported HW and built a platform with standalone A63 core 0 for testing. CDMA transfers data w/o any error flag. The problem is that I read zero only from DDR. I see data in DDR memory (address 0x60000000) but for some reason my CDMA controller transfers zero only. What is incorrect in my design?




      Thank you

        • Re: AXI CDMA problem

          The fault(s) or error(s) in this design are nearly impossible to discover from this set of screenshots.  Rather than starting from scratch, I would suggest starting with a known-good Vivado project.  The instructions at Avnet HDL git HOWTO will direct you to building a hardware platform for the Ultra96-V2 board that you can use as a basis for your CDMA, etc. additions.