I'm looking into this. I've asked Renesas for clarification on their definition as this document shows the 8T49N241 used as a reference clock for the Xilinx Zynq UltraScale+ GTH transceiver reference clock.
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Doing a bit more research on this (haven't heard back from Renesas yet), it appears that the issue is in semantics with how Xilinx is specifying VIDIFF, which is defined as the ZU+ GTH Transceiver Clock Input Differential peak-to-peak input voltage. I think it is very confusing. I feel better knowing that I am only one of many that Xilinx has confused. At some point, we can all hope that Xilinx will change how they specify this in their datasheet. See the following:
If I interpret what I see in these various forum posts, it would appear that Xilinx defines VIDIFF as
[MAX(MGTREFCLK_P - MGTREFCLK_N) - MIN(MGTREFCLK_P - MGTREFCLK_N)]
whereas the Renesas definition is
MAX(MGTREFCLK_P) - MIN(MGTREFCLK_N)
Using some real numbers helps illustrate this. Let's assume an output differential voltage of 200 mV centered around a common mode voltage of 0.9V. That means the signals are swinging between 0.8V and 1.0V.
- When MGTREFCLK_P = 1.0, then MGTREFCLK_N = 0.8V, so MGTREFCLK_P - MGTREFCLK_N = 200 mV
- When MGTREFCLK_P = 0.8, then MGTREFCLK_N = 1.0V, so MGTREFCLK_P - MGTREFCLK_N = -200 mV
- Which then leads to 200mV - (-200mV) = 400mV, which is well within the 250mV minimum spec.
To me, this method of figuring is very confusing, but that appears to be the way Xilinx is doing it. If someone else has a better way of explaining it, please do!
I am designing a carrier card for the UltraZed SOM, and wanted to use a similar design for a reference clock for high-speed SERDES communication as the Avnet Carrier Card design here: https://www.avnet.com/opasdata/d120001/medias/docus/190/UZ-EV-CC-UG-ver1.pdf
Since page 43 of that guide mentions using the 8T49N241 (datasheet https://www.renesas.com/us/en/document/dst/8t49n241-datasheet) in LVDS configuration for one of its output clocks as the GTH reference clock, I thought I would use this component (or the newer 8T49N242).
However, I noticed that, in the LVDS specifications for the output clock in Table 8H of that datasheet, the minimum differential voltage swing of the clock signal is 200 mV, while, according to Table 97 of XIlinx UltraScale+ AC and DC switching characteristics document DS925 (link: https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf ), the minimum differential voltage swing of a GTH reference clock is 250 mV.
Is this not a problem? the minimum differential voltage swing of the clock generator is less than the minimum differential voltage swing required by the Xilinx MPSoC by 50 mV. Does this need to be remedied for reliability?