this isn`t really my area as I have little to no experience with I2C at all, but the Logic graph you show Does make sense to me, and if I understand it correctly, you have a 9`th bit problem.
this can be surpressed with the use of a simple Counter and some glue logic.
effectively the counter starts when a certain logical condition is met, such as your Start.
then will advance the count for each SCLK signal, up until 8.
now From there you you can use the 9`th count to either reset your counter, flash an led
but otherwise be totaly ignored if you have nothing usefull to do with it.
so you`ll need a single gate to intercept your SCLK line, and a counter whos 9`th bit will turn the gate off (leaving your trace flat at that point in the graph).
either way, you`ll need to gate your SCLK and look for a Unique condition that can be met whren that pulse occurs to disable the gate, a quarter of a 74125 with a pulldown resistor may work?
and any number of decade Ripple countes will serve to isolate the 9`th pulse/bit.
hope that helps you Somewhat?
Why do you have the latch? This is certainly not normal for I2C. I2C devices MUST be open-drain so that both master & slaves can pull the SCL and SDA lines down. Remove the latch completely. You can see from your waveforms that the slave is trying to ACK but can't pull down the output of the latch. Anyway how do you expect the master to see the ACK when you have a latch in the way?
So we both agree that the latch is to blame. I’ve been told to keep testing it and basically to make it work as is so I’m not too happy.
I am but a pawn in this institution.
So what I need are smaller pull-ups and less latch...
Thanks for your reply
Thanks for the novel solution but it’s a bit extravagant for my bus. The 9th bit of my transmission is the ACK signal sent by the slave to the master to indicate a full byte received. To generate the 9th bit the master lets go of the SDAT line letting the pull up resistor bring it to 5V then the slave grounds the SDAT line in time for the 9th clock pulse. A zero in place of the 9th bit = ACK a one = NACK.
The problem I was experiencing was that when the slave grounds the SDAT line the latch just pumped it back up again with no possibility of the ACK signal reaching the micro controller.
IF anyone knows of a latch being used in an i2c bus please let me know cause I want to get to be bottom of this.
I am afraid you will never come across an example of a latch being used in this way. Could you explain more regarding the reasoning behind the use of the latch?
The bus actualy does work, I've been using it to control multiplexors, I have had to remove the ACK code since it doesn happen and double up my messages to make sure that they send.
Its half 5 on Friday evening so im out of here
Ima get back onit on monday and maybe pop off the latch to see if we get some i2c going
I’m designing an i2c bus at the moment with an ADuC842 master and a PCF 8574 i2c expander slave. I have a 74HC573 latch in between the master and slave, which I believe to be standard practice.. The problem that I am facing is that I cannot get the acknowledge signal to show up on the master side of the latch. When an ACK is generated by my PCF the pulldown brings the SDAT line from 5 volts to about 2. It shows up quite obviously on the slave side but not on the master side. I am pretty sure the issue is that the latch is not backwards transparent is blocking the pulldown from propagating through to the master side OR the pulldown is not sufficient and the ACK is being detected as logic 1.
Shorting out latch -> didn’t work
Swapping PCF chip -> didn’t work
It would be the job if someone could shed a bit of light on this for me or if you have experienced it yourself..?