After Sixth Sense Design Challenge you may have thought I have gone a bit quite on the community and there is a reason why. This introduction blog lays out my current project plans: I made a suggestion on https://www.element14.com/community/message/271804/l/build-me-an-embedded-processing-system-and-ill-give-you-a-zynq-7000… that the ZC702 board could be used as a Logic Analyser. My comment was thrown in for anyone to utilise, however I was contacted and asked if I wanted to build it....how could I resist the lure of getting to make something on such a powerful board? My background in FPGA is limited but I really enjoyed roadtesting the Digilent ARTY S7 Dev Board (Xilinx Spartan 7) - Review and learnt a lot from that roadtest as well as reading the knowledgeable blogs from the Path to Programmable participants. So, as I always think, what better way of getting more experience than by pushing myself into a new technology....a few days later UPS delivered me a package from rscasny, thank you Randall.
2. Overview of Project Aspirations
I want to make a system akin to an older style Logic Analyser but with modern day protocol analysis as well, that is that it can read 8/16/32 bit parallel data and decode serial data such as SPI, I2C, UART and CAN. I thought that the ZC702 would be really good at achieving this as the ultra fast Programmable Logic (PL) side of the Zynq device would be able to undertake raw processing, saving that data into Block RAM (BRAM) or the DDR memory whilst the 'slower' Programmable System (PS) would enable that data to be processed further after capture and delivered to made available to the end user. I don't have plans for the output to be a fantastic GUI but perhaps add to that at later stages. The GUI may most likely be command line inputs via the controlling UART port to the ZC702.
The parallel and serial decoding tasks are to be looked at separately.
2.1 Parallel Analysis
Sampling the datalines at a very high rate is probably not required: I had a think back to the days when I used Logic Analysers routinely and was sure that an external clock line was specified, and it was that that caused the other datalines to be captured. It would be useful to be able to specify which input line I want to use as the clock from my GUI commands as well as whether I want to use the rising or falling edge to clock in data. It would also be useful later on to be able to trigger on 'words' on that bus, so the data would be sampled and discarded until the trigger word appears or even bits pattern masking in there. Therefore my aim will be to build the FPGA design using BRAM as internal registers that can be adjusted from the PS (and thus from my GUI command line).
2.2 Serial Analysis
In a similar way to the Parallel Anaysis I plan on building the FPGA design to take a single line (and the associated clock, reset etc) and to route them via software configurable (using BRAM) switches to the various IP blocks for decoding, after which that data will be saved into DDR RAM. Most of the common serial protocols are readily available in the Vivado Software Suite, such as SPI, I2C, UART. The system could then be expanded out by adding or writing additional VHDL modules to sit in parallel with those initial serial decoders and to be again GUI selected.
2.3 Voltage Levels and Pins
I have already seen the dire warnings about voltage levels as inputs to the ZC702 and are therefore going to be very cautious about making connections to the board. I want to mitigate against damage as far as possible and therefore will be building an external circuit to step down and limit the voltage. This might be 1.8v or 2.5v and I need to do some investigation as I would also like the circuit to be protected against inputs up to 20v.
3. Setting up and Proving the Design Cycles
It took me a while to get the development system up and running, selecting which version of Vivado to install and getting the license to install wasn't easy as there is a huge range. I believe it is working now and I opted for Vivado 2018.3 although I am prepared to drop back to an earlier version should issues arise. I then set about reading the multitude of reference material before settling on working through the Xilinx UG1165 document. This walked me though some basic examples to prove the Zynq system and Built In System Tests (BIST). Happy with my progress there I started to develop the design myself....some of those didn't work. But my current learning has got me to the following stage where I have the Zynq setup alongside a Microblaze. The later flashes the GPIO LEDs on the ZC702 board. OK, not very interesting I know but this has given me confidence in the whole development cycle and from here I will branch out to try using the other modules that I need, setting values in the BRAM from my GUI commands and observing them effecting the ZC702 operation in real time.
4. Thoughts so Far
It is a very stretching project for me but by building it in small stages I hope to be able to get a very basic system running in the next month and to then build on that. So far I am pleased with how my progress has gone; like anything, the longer you spend struggling along, researching, trying things out, the easier it gets. I'm sure I will add a few changes at some stage and bring the whole dev cycle to a nasty end for a while, I might have to backtrack and try a different approach if that happens. I like Vivado, although I now wish I had spent a little more on my laptop because as an i5/8GByte RAM it does take a noticable amount of time to complete the processing tasks.
Lots to learn, lots to do, lots of hardwork.....but great fun!
I'll keep posting my progress.