Hello all! It's been awhile since perhaps I have posted anything interesting. There are many projects and such I have on back burns that I eventually want to catch up on, but naturally, when i do want to, something that I use frequently and is of great use to me breaks down, an a diversion begins.


Lately I have been doing for 8-bit computing, mainly with the C64 and SX-64 that I have and refurbished to the best of my abilities. I had recently started up making a Tapuino, which the filesystem and and components work fully thanks to the plans from Peter Edwards! Unfortunately, the one component that I didn't consider carefully was the edge-board connector; not because of the pitch, which was fine at 3.96mm, but that there was a separation in the connector pin from supply voltage and ground that were together, and then all the control pins for red, write, motor and sense. A short occurred for which is that best way to describe it and messed up the CIA #2 chip on the C64 Reloaded I have. I had two spares on hand and that did fix the garbage on-screen when I did power up again. Of course, seeing these are old volatile chips, the replacement spare blew out and I had to use my last spare, aside from spending $50 dollars on ebay for another or a fake one from China.   

Block diagram










So that is where this block diagram comes into play. In my studies thus far I am getting into digital logic and I had been curious can a so-called "replacement" chip with FPGA development can happen? So far I had got good feedback from a question I did ask and found out that Xilnix Spartan II or Altera Max 10 would be good candidates to make this happen. The issue isn't so much with the FPGA but more so that this block diagram doesn't make as much sense as I would have hoped for. Schematic symbols are relatively easy for me to interpret, however, I am not certain if this here are block logic symbols, or block gate logic symbols--not sure what I am looking at which makes it rather difficult. I assume the squares are registers, the lines in the center are buses? The access control symbols don't mean  much either.






























The only thing out of the interfacing section are RS0-RS3 which basically address the register that is being accessed; the truth table that was on one of the other pages made sense as to what those pins did.


I guess mainly how I see all this is not so much in code but rather in a schematic format, meaning, that there should be flip-flops and gates of some kind explaining how this chip functions. I get that it talks about its operation throughout and even on this page, however, seeing it in logic gates interconnected as such just would make more sense to me. Again traditionally, from above, I imagine that the squares are flip-flips and somehow interlinked with NAND gates? I suppose I am confused some may be because there are other devices like the processor and SID that this all interfaces to as well and not knowing how it operates in the entire system has me rather overwhelmed to think how one small piece has its place.




I am by no means looking to be spoon fed this, I simply am trying to make sense of this so perhaps I could make some relative replacement and so when this, now 36 y/o technology disappears, some 8 bit machines and still carry on. Just by these two sheets here, I am imagining that I need to concentrate on one pin, as to it's function and find the gate equivalent? Still I am in that schematic design mindset, but that's kind of how I am seeing this all work out.