Two things became very clear to me once I got into the detailed testing of the project:

  • I have completely stuffed up the grounding and layout of the components.  In particular the Switching Regulator has a convoluted route back to Vin -ve and the route it does have takes it right under the sensitive components (until I bodged in a couple of wires).  Layout is too far apart for many components, including the bypass and decoupling caps, and non-conducive to managing noise.  There are no test points with the result that I have blown a number of components including 3 ports on the very expensive 4Duino.
  • I really didn’t have enough knowledge about DC-DC Switching Regulators - I sort of hinted at this in my design post - which becomes clear as you read the answers to some of the advice being given.  In some respects that might be a good thing as maybe I wouldn’t have started on this!  However, I apologise to those who have graciously helped out nonetheless and hopefully I've at least made a start in remedying that.


On the plus side, testing showed that functionally it works so I can get my 0-15V, 0-3A out.  I set about sorting out my understanding so that I could properly layout the board, but also have a much better understanding of how that part of the circuit is working so I can properly probe and test it.  There is excellent coverage of the subject from Micro-Rohm, starting with Switching Regulator Basics, that covers DC-DC switchers in some detail but at the same time keeps the language easy to follow.  There are also a multitude of papers from TI and Analog and the data sheets for buck converter ICs have been helpful - the LT1624 datasheet is still confusing though.


The design is still basically the same, with most changes to the Switching Circuit and Linear Regulator Circuit.


Switching Circuit

Essentially the same but with the following changes (annotated in red):


  1. Test points for the LTC1624 pins and output at the inductor
  2. A placeholder on the gate driver (pin TG) for a small resistor, R2, to adjust the rise time of the MOSFET to help counteract ringing if necessary.
  3. A placeholder for a boost resistor, R3, (pin BOOST) at the switching node to help with ringing there, if necessary.  Possibly a ferrite bead rather than resistor.
  4. A placeholder for a Snubber at the switching node, R5 and C9 ( to help with switching noise if necessary.
  5. A placeholder for a ceramic capacitor on Vout, C15, if I want to experiment with adjustments there.
  6. Upsized the sense resistor to a 1206/500mW part, same 10mOhm resistance.  Takes a bit more area but should be more resilient than the 0805, particularly as I’ve blown it up 3 times!  I’m mostly thinking of ease of replacement.
  7. Upsized the inductor to 50uH: the part I’ve chosen has better specs for resistance, self resonance frequency and saturation current than the original 10uH part (although in fairness, the other part’s specs should have been ok.)  LTSpice simulation shows that ripple on the output - and through the Feedback Circuit - is significantly improved.
  8. The MOSFET is now a SMD component - IRF8721 - with the same (slightly better) specs than the TO220 IRLB8721.


The main concern for the MOSFET was a power dissipation characteristic of only 2W.  I did some soak testing for temperature gain of the existing MOSFET and calculated wattage from that - see below.  The TO220 package doesn’t take up a lot more space than the SMD component (considering just the leg soldering area) but it is a lot more awkward to position and route to.  I did vacillate a bit on this as I know the existing part works : I’ve replaced the existing Mosfet 3 times - once when I blew it up, once when I swapped it for a better part, and once when I de-soldered it for testing when I thought I might have damaged it.


The resistor placeholders R2 and R3 will be populated with a 0 ohm (<5mOhms) resistors initially; R5 and C? will remain unpopulated.  Depending upon what I see during the testing I can populate one of more of these placeholders with actual resistors/ferrite beads and resistor and capacitor in the case of the Snubber.  My understanding is that care is needed with changing the MOSFET timing (BOOST and Gate resistors) as it will increase the switching losses.


MOSFET Temperature Soak Testing

I ran the existing circuit at a range of volts and amps for an hour - 50 mins with the 5Ohm load as I had to leave to do something else and didn’t want to leave it unattended - and captured temperatures at 10 min intervals.  I took the peak temperature for the IRLB8721 MOSFET and using the original Ambient Temperature and the MOSFET’s Tja specification, calculated the power from the temperature rise (temp diff / Tja).  Even in the worst case temperature rise, power dissipation was 0.333mW, well within the replacement's power dissipation rating even after de-rating to 150C.

I’d be very interested to hear feedback on this.  I could switch it back to the TO220 package before I get the board made if I’ve messed up the calculations.


Linear Regulator Circuit

Again, essentially the same but with the following changes (annotated in red):


  1. Test points for the LT3081 pins
  2. Placeholders for addition ceramic capacitors at the input to the regulators, C18 and C19
  3. Placeholders for Ferrite Beads,  R13, R18 and R19, to help with ripple and frequency noise, if necessary.  These will initially be populated with 0Ohm resistors.
  4. Moved the Schottky Diode from the Current Source circuit into the Linear Regulator circuit.


The placeholders for Ferrite Beads are interesting because I have to take into account component sizes as well as their placement on the high-current path.  Scanning around on Farnell, CPC, RS, Digikey, getting a correspondence of size between 0Ohm resistors and Ferrite Beads (at this stage I don’t know if I need them nor what specs if I do) is nigh-on impossible.  So I’ve gone with a 2512 (6.4mmmx3.2mm) size resistor and custom-sized the pads so that 1812 ferrite beads can be used - this seemed to give me the best tradeoff in size correlation.



Hopefully the images I've pasted are viewable but I've attached the Gerbers as well.  With the layout needed, I've gone with a 4-layer board to achieve it - it's a bit more expensive but for the sake of £20-ish it feels worth it given the difficulty of trying to do this with 2-layers, at least that's how I perceive it.  It's also resulted in a slightly larger board at 100mm x 95mm (current version is 100mm x 75mm.)


Layer Stack

Top: components, high current traces, high current ground traces, signal traces

Layer 2: Shield Ground

Layer 3: Signal Ground

Bottom: Signal traces


Test Points

I’ve added in pins for testing of components that have caused me great difficulty in the past:

  • The Switching Regulator pins: I’ve separated out the Switching and Boost pins from the more sensitive pins.
  • The Mosfet gate pin: I will want to be measuring ringing and noise at this point.
  • The Linear Regulators
  • The Current Sense INA260: both Vin and Vout from that chip

I’ve taken the approach of using pins that I can actually either clip a probe to or stick the probe tip into; each has an associated ground pin into which I can insert the short, springy probe ground to avoid have a large ground wire affecting measurements.


Ground Plane vs Star Ground

Before I get into the layers in more detail, I want to start off with this as it’s come up a bit in comments.   As I researched this it became clear that TI, Analog, Micro-Rohm and others all recommend ground plane; however I cannot also ignore Gene’s comments and advice, which comes from experience, to avoid these and use Star Ground.  So where does that leave me: I don’t yet have the experience of implementations (of both approaches) to determine which would be best nor can I make multiple boards with different configurations - the costs are just too high.


So, I have to make a decision and what I’ve gone with is the advice from TI, Analog, Micro-Rohm:

  • All high current ground traces are on the top layer except for two places where I had to go down to layer 2
  • Layer 2 is a Shield Ground which connects solely by the -Ve PCB terminal for Vin.  There are no other connections to this layer.  However, there are vias and through-holes plus the two high current traces that needed to be routed off the top layer.  There is also a Keep-Out underneath the Inductor (L1).
  • Layer 3 is a Signal Ground layer which connects solely by the -Ve PCB terminal for Vin.  There are no other traces on this layer but there are, obviously, connections for all low-current components.   There are also through-holes and vias and a Keep-Out underneath the Inductor (L1).

How does one avoid creating TH 'slots' (holes in a row) in these layers?  I have no idea.  Quite a few come from the test points I’ve incorporated: even using SMD points would require vias for the ground pins unless I avoided those.

I’ve avoided Thermal Vias as testing to date shows that’s not necessary and it would make more holes through the layers.


Check list

Now I have a better understanding of the Switching Regulator, I’ve been able to take a better understanding of layout practices from my reading of data sheet layouts from TI and LT (Analog) as well as the explanation and points presented by Micro-Rohm:

  • Keep the bypass capacitor (Cby1) as close to VDD of the switching regulator as possible.  TICK
  • Keep the loop consisting of Input Cap (Cin1), Sense Resistor (R4), Mosfet (Q1), Schottky Diode (D1) as short as possible.  TICK
  • Keep the loop consisting of Schottky Diode (D1), Inductor (L1) and Output Cap (Cout1) as small as possible.  TICK
  • Traces carrying high currents off the ground plane and away from the sensitive feedback circuit.  TICK
  • Keep the Switching Node - SW pin, D1, L1 and Q1 Source small.  TICK.
  • Use kelvin connections from the feedback circuit connected just after the Output Capacitors.  Vfb should connect directly to the resistors.  TICK
  • Feedback circuit should be connected to the + plate of Output capacitor.  TICK - actually, there are more than one output capacitor and it connects just after the last one as per TI advice.
  • Keep the connections from feedback resistors to the Vfb pin (R6 and R7 - and really also Q2) short and away from the Switching Node.  TICK
  • Gate drive trace should be as close as possible to the Mosfet (Q1) gate.  TICK.  in my opinion - given ‘close’ is relative and I can’t physically get the larger parts any closer!  Part manufacturers don’t help with their pin layout either.
  • Signal and Power Grounds separated.  TICK
  • Does the input capacitor (Cin1) +ve connect to Sense Resistor (R4) as closely as possible. TICK
  • Does Cin1 connect as close as possible to GND pin of Switching Regulator.  TICK - in as much as this makes zero sense as their grounds are meant to be kept seperate!
  • Is ground of Cin1 and Cout1 separated by at least 1-2cm. TICK
  • Is the Inductor (L1) close as possible to the Switching Regulator.  TICK
  • Is the wiring to the Inductor input as small as possible.  Is the wiring distance between the Inductor terminals as great as possible. TICK
  • Are there no ground or signal traces under the Inductor.  Is the Ground Plane kept from underneath the inductor. TICK
  • Are the Inductor and Output Capacitor (Cout1) as close as possible.  TICK
  • Signal and Power Grounds must be kept separate.  TICK
  • Top Layer Power Grounds and Inner Layer Power Grounds must be connected by numerous vias.  TICK (there are only two places where I have routed Power Ground to the inner layer.)
  • Power Ground should be connected to a common ground or signal ground near an Output Capacitor.  NO TICK - grounds and ground planes are connected at one point only near the Power in terminal, based on discussions/advice here.  I believe this point is based on the grounds for the Switching Regulator only, not the 'load circuit' - I have done that with the feedback circuit and IC GND connections.


Quite a substantial checklist but I think I’ve hit them all including the last point.  The grounds are tied at the -Ve pin for VIn but in Kicad I can only do this with a Net tie component - it’s not possible to specify a pin or pad as belonging to multiple nets.  You can see the Net tie in the PCB top layer by the -Ve pin of the PCB terminal.  I think this is ok - any noise from power ground that hits the Shield Ground would route out here.


Silkscreen and Solder Mask

To make it easier to see some of the following images, here's just the silkscreen and solder mask:


Top Layer

(Green traces are bottom layer traces)

High Current traces, shown with green arrows, route along the right, bottom and right side.  Ground traces, shown with cyan arrows route in a similar manner: where I have ducked down to layer 2, dashed cyan arrows, (the Shield Ground) I have used vias to connect the traces - I've just noticed that the fourth short arrow at U3 should be a dashed one.  These are 0.508mm diameter with 0.254mm drill but would it be worth making them bigger?  The check list calls for “numerous” but could I do with fewer of them to reduce via holes through the layers?


Components are placed quite close to each other - much closer than in the last version.  It looks do-able hand-soldering.  In particular, the feedback circuit is well away from the power traces and route through traces to just past the output capacitors.  You can see that I route the GND return under the power ground (on the signal layer) to connect there by the output capacitors as well - it is equally possible to connect at the point it ducks down but I’ve kept the traces together as recommended by the check list.


Shield Ground Layer

This is intended to keep noise away from the non-power components although I could well have misunderstood the concept.  Nothing directly connects to this layer except the NETTIE so it isn’t directly used by anything as a path to ground.  Should I have limited the area to under the high-current traces only?


Signal Ground Layer

This is used as a ground plane by the non-power components - i.e. those not directly related to carrying high-current to Vout.  There are multiple connections on this layer but no traces.  All the cheaper manufacturing companies preclude the use of blind or hidden vias so they all route through 4 layers.


Bottom Layer

This carries signal traces that can’t route on the top layer.  There’s not that many of them really.



I think I’ve made a much better job of laying out and routing the design this time.  The first version was so bad it wasn’t even worth trying to start dealing with the sources of noise but my hope is this will prove capable of proper measurement and action: the placeholders for ferrite beads/capacitors/resistors can at least allow some modifications to be made as a result and the test points will prevent me blowing components up.  I'm more than happy to provide additional information if anyone is interested.


A summary of my questions:

  1. Would it be advisable to swap the MOSFET back to the TH version I used before which is more capable of dissipating power?
  2. Is the use of TH pins for the GND connection with my test points - so I can use the short GND wire on my probe - better than removing those holes through the planes?  Alternatives would be to use SMD test points with vias (smaller diameter) or doing away with GND test points and using the longer crocodile clipped GND wire.
  3. Layout guidance uses a lot of relative terms such as ‘close’ and ‘as possible’.  Is the trace from the Switching Regulator (U1) to the gate of the MOSFET (Q1) too long?
  4. The GND connections for the feedback circuit, Switching Regulator and the ITH/Run pins route around to connect to PWRGND just past the Output Capacitors (one piece of advice read.)  Would it be better to route these directly to the +ve and =ve pads of Cout1 - the 100uF output capacitor (another piece of advice read.)
  5. They don’t just connect to PWRGND just past the output capacitors, they also route under PWRGRND to do so: I could avoid doing that and connect at the point the trace jumps down.  Is it better to leave as-is?
  6. The PWRGND traces all route back on the top layer to the -Ve pin on VIN.  Very close to this point is the single connection for Shield Ground and Signal Ground.  Would it be better placing this nettie close to -Ve pin on Cout1?
  7. The Shield Ground is the full size of the board.  Should I just place this under the high-current routes or does it not make any difference?
  8. From experience, does this look hand-solderable if care is taken with the order of placement of components.
  9. I have no copper fills on the front or back layers.  If I added these and tied them to the nearest ground plane the vias would pass through all 4-layers.  Ultimately, I don’t know if it would improve anything so I didn’t bother as more holes in the layers seems ‘a worse thing’ but am I wrong?


I’d be very interested in thoughts and observations on my approach so I don’t make the same mistakes as last time.  In particular, given that grounding was a major issue in the current version, what’s your views on how I’ve done this time.


Next: Part Twelve Reprise - Design revisited

Back: Part Eleven - Further Testing