Hello there,

 

Lately I have been working a lot with filter design and implementation on FPGA.

As you know the most common way to design a filter is through MATLAB or a suite with the similar capabilities.

Either way the produced result is an array of floating point values. FDAtool has the ability to translate the values from decimal

to binary floating point, however, if the implementation is in fixed point, then this functionality is useless.

In order to make use of the coefficients, they have to be represented as 2's complement.

At first I used to translate each value by making use of the online decimal-to-2's complement converters, but as you can imagine

this can get quite tedious. To combat this problem I developed a simple Python program, which does the whole work (almost) in a click of a button.

 

 

The concept is quite simple:

 

1.Browse to the filter coefficient file (.fcf) or any other file containing decimal values that range between 0.999 and -0.999.

There has to be only one value per row!

 

2. Chose the desire structure of the output file.

2.1 Array will return the data enclosed in a VHDL, Verilog or C array. The options to select the language are available only for the array option.

2.2 List will return a list of values. Chosing this option gives the user the opportunity to enter a separator between the values.

 

3. There are 4 possible output formats - binary, hexadecimal, signed and unsigned integer.

All of them represent the equivalent of the 2's complement value.

 

4. Elements per line determines how many values are ther per row in the output file.

 

5. Output bit width determines the desired bit length of the output product.

If the selected format is hexadecimal and the selected bit width is not multiple of 4, then the output width will be extended to the next value multiple of 4.

 

6. File extention sets the type of the output file - typical choice is text (txt), however, by using a data format (data), the user can

create a list of values that can be used to initialize block RAMs in Vivado.

 

7. The Translate button creates the output product.

 

8. The console in the bottom displays various information such as data that has been rejected by the translator in the form of warnings,

tips about the input file, and errors.   

 

Done!

 

Here is a video demonstarion:

 

 

You can it from my Github.

Enjoy