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Its been a while since i uploaded a post about the Systems Project, so sorry if this is a bit longer than normal.   We currently have nine days until the build need finished for display at the presentation. So we are all trying to get this done quickly as we also have our exams coming up in two weeks time.     The main design consists of two towers to hold the blocks. Each tower can hold about 10 blocks.    For Sorting the blocks into the towers we have a small p ...
This Weeks Deliverable is to drive the servos connected to the FPGA from the PC, In normal operation, this would be done with the Mbed in the middle. ALthough for getting it up and running I have modified our Maintenance Software to output Hex Values for the FPGA to Read.   Apologies for the poor quality Video     The main bulk of the verilog source, attached, has already been written. The Servo driver was completed for an assignment several weeks ago. The UART receiver has co ...
I thought I would share this project that I have been working on for about six years, on and off. It is a controller for four aspect model railway signalling. Functionality of four aspect signals   When most people drive these signals on a layout, the will use a rotary switch to change the signal, but when you have a layout with multiple of these signals, the control board becomes very cumber sum and hard to maintain.   When I first designed the controller I designed it for use on ...