It doesn't have to be silicon all the time. I have a Gallium-nitride device here at the Cumps lab that I'm going to try out. In some high voltage, high power designs, GaN FETs have advantages over Si. On the other hand they are also more difficult to drive.
The chip that I have contains a built-in smart GaN FET driver. That takes away the complexities of driving the power stage correctly. We're covering fairly new technology here. The documents are still marked technology preview. I received them from TI after attending a GaN seminar and answering right on the quiz.
In this post I'm probing the switching output and checking the dead time between switching transitions.
The Switching Node Output
Taken from the technology preview document lmg5200.pdf.
The switching node (pin 8, SW in the schema above) is the output tab between the upper and lower half of the half-bridge.
It's the power output signal - driven high and low by the two output FETs to generate the final PWM.
Between the transitions there has to be some dead time - a time when it's guaranteed that both sides of the bridge are shut off.
To allow fast switching times, it's key to optimize the dead time. It should be long enought to ensure stability, but no longer.
In an optimal configuration, one side of the bridge is always on and one side off.
Dead time eats away from that optimal situation and limits the maximum PWM frequency.
|What is Dead Time?|
Definition from Infineon AN2007-104 Dead Time Calculation for IGBT modules (this applies to GaN modules too):
In order to avoid bridge shoot through it is always recommended to add a so called “interlock delay time” or more popular “dead time” into the control scheme. With this additional time one IGBT will be always turned off first and the other will be turned on after dead time is expired, hence bridge shoot through caused by the unsymmetrical turn on and turn off time of the IGBT devices can be avoided.
The GaN driver that I'm using here, where the driver logic is built into the same package as the GaN power FETs, allows for dead times smaller than 10 ns.
On my evaluation board, the dead time is configured to be approx 8 ns. Let's probe that!
The evaluation guide of my board gives a detailed overview of how to do these measurements.
We're talking about fast edges here, so our test setup has to be done right to avoid introducing parasitic inductance via our probe.
Ever wondered why there's a spring in the accessories bag of your scope? It's there to do measurements like this, at frequencies where the ground wire of the scope can act as an extra inductor or as a noise antenna.
The ground spring minimizes that loop.
I've measured two signals: the dead time when switching the output from low to high, and - just for kicks - the rise time of the output PWM.
I'm measuring a dead time of 7.2 ns. Almost the 8 ns specified in the doco.
The rise time - measured just before the output LC filter, with 1 amp output load, 50% duty cycle, is 3.8 ns.
We're dealing with a fast switcher here. That opens new opportunities for small high-power switching.
But it's also going to cause some headaches on the EMF compliance front.
|Part 1: Preview|
|Part 2: Dead Time Capture|
|Part 3: Control Deadband with Hercules LaunchPad|
|on TI E2E community: driving GaN with a simple PWM signal|