We know SPI as a 4*-wire protocol. But it doesn't have to be.
I'm checking high speed SPI data transfer with buffers, DMA and parallel data lines.
While I'm at it, I'm also going to test hardware handshaking with the Enable signal. Let's see if we can get decent speed.
High Throughput Requirements
SPI (Serial Peripheral Interface) as a serial protocol can be reasonable fast.
In its purest form, where we have bidirectional traffic, the limits are set by the speed of the clock and the speed at which source and destination can provide and consume data.
For many sensors, common SPI with low frequencies s good enough to exchange data.
That changes when we're trying to talk to displays and other peripherals that need big data.
There are mechanisms that we can deploy to deal with throughput inside our microcontroller.
We can use DMA and interrupts, so that the handling of the traffic can be done in parallel with other microcontroller tasks.
That frees up the processor to collect or create the required data, while its SPI module handles traffic independently.
If we apply this method in a right way, we can in many cases take care that the communication buffer has enough data to keep the throughput high.
But that still leaves us with the limits of how many bits you can rush through a single data line.
The clock is telling how many single bits we ca bump onto the traffic track.
The industry has come up with a solution that breaks the one bit per tick paradigm: multiple data lines.
That may be odd, because the name of the protocol indicates it's serial, and multiple data lines are parallel.
If that bothers you , you can call it PPI and live happy ever after.
High Throughput Goals
In this blog series, Ill try to get 50 Mbits per second transferred through the SPI interface.
The hardware that I have available has DMA, SPI memory buffers and 4 data lines for MISO and MOSI.
Theoretically, based on the maximum SPI clock rate my controller can have, I should get 80 Mbits.
|The SPI clock is 20 MHz. I have 4 data lines, so 4 bits per clock cycle: 80 Mbits /s|
Reality will also play a role. It 'll be tough to prepare and consume actual data at that rate.
The test bed will do everything to keep our SPI buffers full enough to achieve an as-close-to-theoretical throughput as possible.
50 Mbits is a good 60% efficiency. Let's see if we can achieve that...
* there's also 3-wire possible
|0 - Buffers and Parallel Data Lines|
|1a - Buffers and DMA|
|1b - SPI without Buffers|
|2 - SPI with Buffers|
|3a - SPI with DMA|
|3b - SPI with DMA works|
|4a - SPI Master with DMA and Parallel Data Lines|
|Hercules microcontrollers, DMA and Memory Cache|