In this post, I test the slew rate of the DAC8775, the subject of the Quad-Channel, Analog Output Module RoadTest.

The edge of the DAC generated signal is programmable. Let's look at how to control it.

 

 

Configurable Slew Rate

 

One of the options you can set on the DAC is the speed at which the signal changes. Depending on your application this can be useful.

By default this control is switched off and the DAC tries to reach the desired level as fast as it can.

The image below shows the DAC going from 0 to 5 V without slew rate control.

The resistive load for the tests is 330R. The capacitive load for my tests is unknown, but in essence the inherent output capacitance of the DAC in parallel with PCB traces, 2 patch wires, a few breadboard contacts, scope probe and scope input.

Except for the first test where the slew rate is uncontrolled, the capacity should be neglectable.

edit: I just saw that there's a 0µ1 capacitor on each DAC output on the EVM. I did not know that when writing this article.

 

 

According to the spec the rate is 1 / µs

In my circuit the rate turns out to be 34µs for 5 V: 0.15 V / µs. There is capacitive influence visible.

 

What I'm trying now is to control that slew rate. For the sake of this blog, I'll use a very slow rate.

You can configure 3 parameters

  • slew rate control enabled / disabled
  • how many steps does the DAC take each time it moves toward the desired value. This can be chosen between 1 bit steps up to 128 LSB steps
  • how fast the DAC makes those moves, in Hz. Configuarable between 3.3 kHz and 258 kHz

 

In my program, I set the clock rate to 131145 Hz (11:8 0011), and 1 LSB (7:5 000).

Note that I also set byte 12, because I switch the output on in the same command.

Bitwise:

 

0000 0100    0001 0011    0001 0000

0x04          0x13          0x10

 

    TX_Data_Master[0] = 0x04;
    TX_Data_Master[1] = 0x13;  // output on, slew rate 131,145 Hz
    TX_Data_Master[2] = 0x10; // slew rate on, step: LSB

 

In theory, this should lead to a 100% ramp from 0 to 5 V in 253 ms:

clock: 65535 steps (0xff)

That is 1 LSB increase each (1/131145) each 7.62514773723741 µs.

Time from 0 to  V -> 500.636699836059 ms

 

A scope calculates the time from 10% to 90% for rise time. Because our increase is linear, I can calculate 80% of the time to get a similar figure: 400.509359868847 ms

 

Here is what the scope thinks: 415 ms.

 

Good enough .

 

Next time, hopefully Current Mode

 

 

 

Related Blog
DAC8775 Quad-Channel DAC EVM - unlicensed roadtest part 1: Raw SPI
DAC8775 Quad-Channel DAC EVM - part 2: Firmware
DAC8775 Quad-Channel DAC EVM - part 3: Slew Rate Control
DAC8775 Quad-Channel DAC EVM - part 4: Current Mode
DAC8775 Quad-Channel DAC EVM - part 5: HART Interface