It seems 2018 is going to be the 'Year of the FPGA' here on element14 ('Forward Heroic Engineers of the World to a Flip-Flop Rich Future'), so I thought I'd join in, buy a small development board and do a simple project or two. The board I'm working with here is the Brevia2 board from Lattice[2].


Part 1 covered unpacking the board, connecting it to the computer and checking that it worked:


Booards and Boojums: Lattice XP2 Brevia2 Board: Part 1


In this part I'm going to try doing a very simple design in VHDL using the development tools (Diamond 3.10). Nothing too complicated - I'm just going to count in binary on the row of LEDs in the bottom corner. This will allow me to run through the design flow and see how similar the process is to what I've used before (Xilinx WebPack). Just for fun I'm going to see how far I can get without looking at the help files and other documentation.


Here's how the IDE looks at first start-up.



It's the usual sort of thing. There's a large pane for editing files in, a pane to the left shows various views of the project, and a terminal area at the bottom takes output messages from the various programs that operate behind the scenes to do the synthesis and mapping. Here are pictures of the files and process panes:






I created a new project (Files->New->Project), setting the destination directory and the part type. Then I selected the files view, left clicked on Input Files, and selected (Add ->New File) to give me a VHDL (.vhd) source file to work with. Double clicking on the filename loaded it into the editing area and I entered my first go at the VHDL to get the LEDs to count. After sorting out a couple of syntax errors where I'd misstyped things, I had a green tick against 'Synthesize Design' on the process pane and then had a go at double-clicking 'Map Design' and 'Place & Route Design'. That all went fine. I then found that I could bring up views of the placement ('Floorplan View' and 'Physical View') using buttons on the toolbar. So I had a design fitted to the FPGA. There was just one snag (there always is a snag somewhere along the way when you're hunting a snark), the mapping didn't know anything about the external hardware on the board and had just randomly assigned the IO pins.


Hmm. There didn't seem to be a tool (that I could see) for setting the pinout, but the files view had a constraints file entry so I looked in the Lattice example project for the board and, lo and behold, there was a .lpf file that had entries for the pins, giving pin numbers and other information. I copied it all to my .lpf file and adapted my VHDL to use the pin names. (I also took the precaution of tying the control signals for the SRAM, SPI memory, and the UART tx line to fixed levels in my VHDL so they would be inactive.) After rerunning the synthesis and mapping, I then found I had a floorplan where the correct pins were being used. (There's probably a better way to set up the pinning than this, so I guess I'm going to have to read the documentation at some point.)


Final step was to see if I could program the FPGA. I ticked the box next to 'JEDEC File' on the Export Files section of the process pane (since that was the only option in view that might serve for programming), double-clicked 'JEDEC File itself and the software then produced the file for me. I hit the Programmer button on the toolbar, changed the settings to use the FTDI programmer, and then hit the program button.


The FPGA was programmed and I saw the LEDs counting. Except I didn't; shame to say, I'd made a mistake in the code and had to go back and rework the VHDL. Then it worked and here's the video to prove it: