Another difference between an ordinary oscilloscope and a mixed domain oscilloscope comes down to the presence of digital input channels. In the case of the RTM3004, the RTM-B1 Mixed Signal option provides 16 digital channels to turn the RTM3004 into a mixed domain oscilloscope.
The digital logic channels are connected to the right-hand side of the oscilloscope through two coax-ribbons which connect to two identical pods hosting eight channels each. As for which pod is designated the “high” or “low” byte, this depends on which port it is connected to on the oscilloscope. The other sides of the pods are connected to break-out cables which allow for connection to individual bus lines and ground lines. Each signal line can be individually grounded for the best signal fidelity, with provision for each pod to be grounded through one or two connections for convenience. The relevant cables and test clips are included in the bundle. To see the hardware, refer to the unboxing in Chapter 2.
Each of the logic channels has an input impedance of 100kΩ || 4pF which is not as high as the analog channels but very sufficient for most digital signals. It is capable of up to 400Mhz input frequency and 0.5 to 40V peak-to-peak swing with configurable threshold ±8V in 25mV steps and hysteresis. The system is capable of measuring at 2.5GSa/s on both probes or 5GSa/s on one, with 40Mpts memory for every channel using both probes or 80Mpts memory for every channel with just one probe.
While some people seemed to have an objection to the channels coming out of the side of the oscilloscope, I didn’t find this a particularly problematic arrangement as there should be clearance of at least 10cm on all sides for ventilation anyway. The flexibility of the coax ribbons and their length provided versatility in positioning compared to some shorter digital probe cables connected to the front panel of other oscilloscopes. One possibility was to have the RTM3004 propped up on its front flip-out feet and thread the cable behind and underneath the unit for a relatively compact arrangement. Having two pods of 8-bits each allows for ease of positioning when probing two distinct separated buses. The digital channels can be used in parallel with the four analog channels for a total of 20 channels and protocol decoding is also possible on the digital channels.
Experiment: Uno32 Linear Feedback Shift Register
For the first test, I decided to drive all 16 digital lines from the outputs of a Uno32 simulating a 16-bit maximal LFSR and one analog input with a toggle clock (more details, see Appendix). I used cheap no-name prototyping “Dupont wire” connections using just one shared ground for each pod. The colours were somewhat random, basically what I had at hand.
I had the logic probe ribbons fed underneath the oscilloscope, and the setup was quite neat given the number of connections involved.
The digital channels are denoted in blue on the display and can be independently moved and scaled. In the toolbar at the bottom, the status of the channels is also indicated – in this case they are all denoted as toggling as expected. In this case, I also have an analog “clock” channel active showing how the channels can be used together. The trigger point is at the state where all ones are appearing at the output of the LFSR.
This was achieved by using the pattern trigger mode which allows you to specify a bit-pattern to look for combined with a particular condition – in this case, width.
While the Uno32 only puts out about 1Mhz update rate, I wanted to test the RTM3004, so I set about doing an extended capture spanning about 60ms.
Zoomed in, it’s still easy to see the detail – the digital channels clearly show three distinct change times with correspond to the bit-arithmetic of three separate ports required to produce the output. Given that 625MSa/s was still being achieved, being able to see this detail is probably no great surprise but illustrates the importance of memory.
Experiment: Digilent Nexys 3 Linear Feedback Shift Register and Counter
A 1Mhz signal wasn’t going to stress the digital probe, so I decided to take things further and employ a Digilent Nexys 3 FPGA board to generate much faster signals clocked at 100Mhz and 200Mhz.
The same Dupont wires were reused from the previous set-up, with the exception that two grounds are added per pod to reduce the ground impedance. As the Pmod connectors have two grounds each (i.e. no individual per-signal ground), I didn’t expend additional effort to add extra grounding. The spaghetti wiring and random routing of wires probably didn’t help, especially when attempting to push 100Mhz signals through.
Before testing the digital probes on the signal, I wanted to verify that the signal itself was “integral enough” for testing. For this, I turned on persistence mode and connected one of the LFSR outputs to an analog channel. This formed an eye diagram – there is an opening, indicating that the signal isn’t entirely corrupted, but it seems to look more like a 4-level signal rather than the 2-level that it actually is. This is probably due to a number of factors, mostly originating from my slap-dash FPGA design which violates maximum simultaneous output switching, capacitance in the wiring and connections, impedance mismatches due to random routing of wiring, etc. Still good enough for a trial.
Triggering again at the point of “all ones” output, we can see that it is possible to get some fairly detailed measurement of pulse width. It was discovered that persistence mode does not seem to affect digital channels making visualisation of jitter less convenient. This has been reported to Rohde & Schwarz for improvement.
This time, I decided to repeat the same experiment, instead focusing on capturing 12ms of data and demonstrating the search function. Using the pattern search, it is possible to search inside the memory buffer for events.
As the LFSR has a total of 216-1 states (i.e. 65535 states) clocked at a rate of 100Mhz (10ns/state), we expect it to reach the all-ones state every 655.35us. Indeed, the event table says exactly that.
The event table allows you to select a search result and zoom in on it directly – we can clearly see that is the “event” we are looking for.
To stress the unit even further, I decided to use my 16-bit counter design clocked at 400Mhz to produce 200, 100, 50, 25 … Mhz output signals.
The unit does display some aliasing effects when changing the timebase to the longer ones – at a timebase suitable for viewing the slowest of the counter outputs, the fastest outputs are aliased. This is not unexpected, as many digital storage oscilloscopes do exhibit this behaviour due to the order and method of data decimation, but I have reported it in case it can be improved. Once zoomed in, some glitches (e.g. skew and runt pulses likely due to propagation time differences) due to my poor FPGA design and grounding practices are visible, but 200Mhz is still captured well by the probe and it is actually providing some insight into what's happening.
Having the RTM-B1 Mixed Signal option is highly recommended if you intend to do mixed-signal work that requires the parallel monitoring of multi-bit digital buses. The hardware offers impressive specifications including the ability to monitor signals up to 400Mhz running between 0.5 to 40V peak-to-peak with a threshold that can be set ±8V in 25mV steps and adjustable hysteresis. It offers 40Mpts on every channel when running with all 16-channels enabled or 80Mpts when running with 8-channels enabled. The digital channels can work together with the analog channels to bring up to 20 simultaneous channels and protocol decoding on the digital channels is also possible. The use of a relatively long coax ribbon with external pods that can easily be detached allows for more versatile positioning of the oscilloscope and device under test which can be quite helpful especially if working on larger equipment.
During testing, I found the digital channels to work well and I was not able to push them to their absolute limits owing to the difficulty in generating and conveying a 400Mhz signal to the unit. Testing was performed on a counter at 200Mhz and an LFSR at 100Mhz which was easily successful demonstrating the memory and search capabilities. The probe was also capable of identifying timing jitters and glitches due to deficiencies in my FPGA design owing to the quick-and-dirty design methods employed. The only issue appeared to be that persistence does not seem to affect the digital channel displays, which has been reported to Rohde & Schwarz.