|Product Performed to Expectations:||9|
|Specifications were sufficient to design with:||8|
|Demo Software was of good quality:||7|
|Product was easy to use:||7|
|Support materials were available:||8|
|The price to performance ratio was good:||8|
|TotalScore:||47 / 60|
In this RoadTest, my intention was to go through some examples with the Zybo Z7-10 and then attempt to get the Xilinx reVISION software running on the board with OpenVC, however that ended up being too heavy of a lift for me at this time to port the demos to the Zybo Z7-10 where they were designed for the Z7-20 board. I still plan on working to get the reVISION software to work with the Zybo Z7-10, but for this RoadTest, it will be left out so I can get this in at the prescribe deadline. I'll continue to post my progress with this though.
What I plan to cover in this RoadTest are:
The Zybo Z7-10: Zynq-700 ARM/FPGA SoC development board offers a variety of options with multiple on board switches, buttons LEDs, 5 Pmod connections, HDMI in and out, Ethernet and much more. The Zybo Z7-10 is a step up from a Basys 3, in that the Z7-10 with the Zynq processor offers bot the Artix-7 Programmable Logic (PL) capabilities as well as offers an Processing System with a ARM processor that can be booted with a Linux kernel. The PS and the PL of the Zynq processor can be utilized together to create an very flexible platform that can be used in multiple projects.
Digilent Zybo Z7 product page:
Some of the Specs for the Zybo Z7-10 from the Digilent site:
|PS||667 MHz dual-core Cortex-A9 processor|
|PL Equivalent||Artix-7 FPGA|
1GB DDR3L with 32-bit bus at 1066 MHZ
16 MB Quad-SPI flash
|Look up Tables (LUTs)||17,600|
|Block RAM||270 KB|
|Total Pmod Pots||5|
|Programming options||USB-JTAG, Quad-SPI flash, and microSD card|
|Power||USB or 5v Wall Jack (For Pcam 5c and microSD card boot, the 5v barrel jack is the best option)|
|Ethernet||Gigabit Ethernet PHY|
|Camera support||MIPI CSI-2 support|
|Switches and Push-Buttons|
4 slide switches
6 push-buttons (2 processor connected)
Specs for the Pcam 5C
|Connection||Dual Lane MIPI CSI-2 image sensor interface|
|Resolution||Supports QSXGA 15Hz, 1080p@30Hz, 720p@60Hz, VGA@90Hz, QVGA@120Hz|
|Output Formats||RAW10, RGB565, CCIR656, YUV422/420, YCbCr422, and JPEG Compression|
Lens replaced with: Vicdozia 2.5mm Replacement 170 Degree Wide Angle Camera DV Lens
|Cable||10 CM cable|
The Zybo Z7-10 kit only comes with the board and no USB or Power Adapter is provided. These are required to use the board, and a Power Adapter is needed if a MIPI camera is attached or the board is booted via the micoSD card.
The image above shows the Zybo Z7-10 and how the options are laid out on the board. There is a missing Pmod header at JB, but this is only provided on the big sister of the board the Z7-20. For a beginner or student leaning about FPGA design, the Z7-10 is a great board to start with. There are plenty of options to interface with the board and the Pmod headers allow for multiple Pmod sensors to be attached to the board.
The Pcam 5C is shipped with the 10cm cable pre-installed, however this was later replaced with a 30cm cable. Also, the Pcam 5C has a fixed focus standard lens which was replaced by a Wide angle lens. The Pcam 5C attaches to the Z7-10 via the J2 MIPI connector in between the two HDMI interfaces. The Pcam 5C along with the Z7-10 provides a nice, yet limiting, platform for experimenting with computer vision or object detection. There is a Pcam 5C demo that demonstrates the Pcam 5C functioning later in the RoadTest Review.
The Digilent page for the Zybo Z7-10 has links to a number of demos and examples that cover Xilinx Vivado, SDK, Petalinx, Pmods and other options. However, some of these examples and demos were written for a particular version of software such as Vivado and can take a bit of work to get them migrated to a newer version of the software or the install of an older version of the software. The Blinky example, a.k.a. Getting Started with Vivado, is a good place to start since it can be run with the latest version of Vivado, such as 2019.1.1 (2019.1 with Update 1). This example walks through the steps to created a basic Verilog program that can loaded on the Z7-10 to blink the on board User LED. Vivado 2019.1.1 was used in this example.
After installing Xilinx Vivado Design Suite, it is necessary to install the board files that include support for the Zybo Z7-10.
These can be obtained from the following:
After, downloading the board files zip file, uncompress the file and place the associated board files in the Vivado board_files folder.
The folder for the Zybo Z7-10 will be labeled : zybo-z7-10
Once the board files are in place, launch Vivado.
If on Linux, it is required to source the appropriate settings scripts.
source /opt/Xilinx/Vivado/2019.4/settings64.sh vivado
1. Select Create Project under Quick Start
2. Select Next to proceed
3. Choose a Project location
4. Set a project name
5. Set the Project Type to RTL Project
6. For the Default Part, select Boards and then find and select the Zybo Z7-10 listing and click Next.
NOTE: If the Zybo Z7-10 is not listed, then ensure the board files have been properly installed.
7. A New Project Summary window should appear listing the project details.
8. A Create Project process bar should appear
9. If successful, the Vivado Project Manager window will appear.
10. Add Constraints files
Digilent has created the associated constraints files for their boards. The need to be downloaded and installed.
11. Save and extract the files on the computer
12. From the the Flow Navigator-> Project Manager window, select "Add Sources" to add the constraint file.
13. Under Add Sources, select "Add or create constraints"
14. In the Add or Create Constraints window, select Add Files .
15. Select the Look in folder and select the appropriate constraints folder.
16. Select the Zybo-Z7-Master-xdc file.
17, Next, select Next to add the constraints file to the project.
18. The constraint file should appear in the Sources window.
19. Double click the Zybo-Z7-Master.xdc file to open it for editing.
20. In the constraints file, near the top, under the "Clock signal" heading, comment the set_property and create_clock entries.
Ensure the clock variable in "get_ports" set to "clk".
21. Scroll down the file until the LEDs section is found and uncomment the entry for "led". This should be the first entry in the list.
Change "led" to just "led" in get_ports.
22. Next click Add Sources and then select Add or create design sources to add a source file to the project.
23. The Add or Create Design Sources should appear. Click Create File to create a file.
24. In the Create Source File pop-up, set the File Type to Verilog and File name to blinky.v, or a name of your choosing and click OK..
Leave File location to "<Local to Project>".
25. The new file should appear in the Project Manager window.
25. Open the file and there should be some default code already populated in it.
26. Add the following code between the ");" at line 25 and endmodule at line 27.
reg [24:0] count = 0; assign led = count; always @ (posedge(clk)) count <= count + 1;
The code should like similar to the following:
27. Once the project has been saved, click Run Synthesis to start Synthesis and Implementation process.
Leave the options to their defaults.
28. Once the Synthesis process has started, the status at the upper right of the window should change to indicated the stage of processing it is in.
29. Once the Synthesis is completed, a pop-up should appear to move to the Implementation phase. Click OK to continue..
30. Select the defaults.
31. Again, the status at the upper right of the window should indicate the project is being initialised.
32. Once complete, a pop-up will appear. Select Generate Bitstream to create the bit file that will be loaded onto the board.
33. Select the defaults.
34. Once the Bitstream creation is complete, another pop-up will appear. Select, Open Implementation Design to start the board program process.
NOTE: Ensure the Zybo Z7-10 is connected to the computer via USB and the power is switched on.
JP6 Should be set to USB
JP5 Should be set to JTAG
35. The Nets will be read in.
35. From the Implemented windows, select Open New Target to open the device.
36. This will guide through opening the Zybo Target device.
37. Connect to Local Server
38. The Digilent xilinx_tct JTAG device should be listed.
39. A Summary window will appear.
40. This should start to open the target for programming.
41. The Zybo device should now appear in the Hardware Manager window. Select Program Device.
42. A pop-up window should appear listing the Bitstream file created previously.
43. Select Program and the device will be programmed with the bitstream file and LED0 on the board should start blinking.
Video showing the Blinky example running on the Zybo Z7-10
Download the Degilent Pcam 5C demo from the following GitHub repo.
NOTE: Release Zybo Z7-20 Pcam 5C Demo Vivado 2017.4.
Download the file Zybo-Z7-20-Pcam-5C-2017.4-1.zip not the source files.
2. Unzip the file and either run Vivado with a source to the create_project.tcl script or start Vivado and then select the tcl console at the bottom of the start page.
vivado -source proj\create_project.tcl
This will start vivado and create the project according to the create_project.tcl script. You only need to do this once.
2. After Vivado is up and running, the Zybo Z7 part needs to be changed to reflect the Z7-10 board.
Select Edit under Settings.
NOTE: Do do this before any updates to the project.
3. In the Settings window under General, click the "..." to see a list of boards.
4. In the Select Device pop-up, select Select Z7-10 (xc7z010clg4000-1) under Display Name.
5. Once the correct part has been select, it should not appear under Project Summary.
6. Click on Open Board Design and then double click on the MIPI_CSI_2_RX_0 IP block.
NOTE: MIPI_D_PHY_RX_0 is shown selected but the CSI to the right of this.
7. Disable Debug Module and click OK.
8. If a message appears stating the block is locked, then perform this step after the IP Status update.
9. Click the Report IP Status at the top of the window and then Update Selected in the
10. If successful, an IP Upgrade Complete pop-up should appear.
11. It maybe necessary to create an HDL Wrapper for system_i and set it to the top level.
12. Just take the defaults options
13. Save the project and select Run Synthesis in the Flow Navigator. Take the default options.
13. Once the Synthesis is complete, Run Implementation
14. Take the defaults.
15. If an error is seen for DVIClocking, then perform these steps.
digilent zybo [Synth 8-439] module "system_DVIClocking_0_0" not found
Manually edi the following file.
Change the following entries so the Vivado version is 2017.4 and the Part is for the Zybo Z7-10 not the Z7-20.
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.4</spirit:configurableElementValue>
If on Linux, start Vivado as :
vivado -source proj\<project_name>.xpr
From this point, just follow the steps starting at step 3 listed in the "Zybo Z7 -20 Pcam 5C Demo" GitHub README.
1. Export the Hardware Design
2. Export and Include Bitstream
3. Once the Hardware is exported, from Vivado, launch the SDK.
4. Set both options to <Local to Project> and not the locations shown.
5. Create a Application Project with Project name set to: pcam_vdma_hdmi
6. Select the Empty Application Template:
7. Expand the pcam_vdma_hdmi folder and right click on 'src' and select Import.
8. Select General->File System
9. The project should look as such.
10. From the Xilinx menu options, select Program FPGA to send the Bitstream to the FPGA.
NOTE: Open a serial connection to the board using a tool such as PuTTY or minicom with a baud rate of 115200.
Ensure the Board is powered by a 5v Power Adapter and the following jumper settings are set and the board is powered on:
JP6 - Should be set to WALL
JP5 - Should be set to JTAG
11. Right click on pcam_vdma_hdmi and Run As -> Launch on Hardware (System Debugger).
12. Click Ok for FPGA Configuration
13. The SDK Console show show Program FPGA and the SDK Log window should show the Launch script output.
14. If all goes well, the serial screen will display a menu of commands to run to control the Pcam 5C from the Zybo Z7-10.
15. Select an option to change the Pcam settings.
Picture showing the Pcam 5c demo running on the Zybo Z7-10 and with HDMI output to a small HDMI screen.
16. Video demonstrating the Pcam 5C demo on the Zybo Z7-10.
One of the cool options of the Zybo Z7-10 is that it has a Xilinx Zynq processor that not only includes a Programmable Logic FPGA part but also a Dual core ARM Cortex-A9 processor. This allows the board to be programmed with a Linux kernel which can be used in conjunction with the PL side of the Zynq processor. To get started with programming the board with Linux, Digilent provides a Petalinux example that can be built and loaded on the board; Zybo Z7-10 Petalinux BSP Project. To build and program this, Xilinx Petalinux and SDK 2017.4 was used.
NOTE: If using a Linux VM, ensure it has at least 4 CPUs assigned to it.
OS: CentOS 7.6 was used for this.
Set the following in the user home directory if using Linux
$ cat ~/.xsdbrc configparams-sdk-launch-timeout 600
Set the following if using Linux.
$ export SWT_GTK3=0
NOTE: Ensure the Zybo Z7-10 is connected to the computer via USB and the power is switched on.
JP6 Should be set to USB
JP5 Should be set to SD
Build and install image
1. Download and unzip the v2017.4-1 BSP file Petalinux-Zybo-Z7-10-2017.4-1.bsp.
NOTE: It might be necessary to clear the Xilinx files if a previous version was used.
$ rm -rf ~/.Xilinx/ $ rm -rf ~/.Xil
2. Ensure Petalinux and SDK 2017.4 have their setting files sourced.
$ source /home/fpgauser/PetaLinux-2017-4/settings.sh $ source /opt/Xilinx/SDK/2017.4/settings64.sh
3. Run petalilnux-create against the BSP file to create the project
$petalinux-create -t project -n Zybo-Z7-10-2 -s /<source location>/Zybo_Petalinux/Petalinux-Zybo-Z7-10-2017.4-1.bsp
4. Change directors to the project folder and run petalinux build to build the code.
$ cd develop/zyboz7/Zybo_Petalinux/Zybo-Z7-10-2 [fpgauser@fpgadev Zybo-Z7-10-2]$ petalinux-build [INFO] building project [INFO] sourcing bitbake INFO: bitbake petalinux-user-image WARNING: Host distribution "CentOS-7.6.1810" has not been validated with this version of the build system; you may possibly experience unexpected failures. It is recommended that you use a tested distribution. Loading cache: 100% |############################################| Time: 0:00:01 Loaded 3257 entries from dependency cache. Parsing recipes: 100% |##########################################| Time: 0:00:05 Parsing of 2473 .bb files complete (2434 cached, 39 parsed). 3266 targets, 226 skipped, 0 masked, 0 errors. NOTE: Resolving any missing task queue dependencies Initialising tasks: 100% |#######################################| Time: 0:00:17 Checking sstate mirror object availability: 100% |###############| Time: 0:00:07 NOTE: Executing SetScene Tasks NOTE: Executing RunQueue Tasks fsbl-2017.4+gitAUTOINC+77448ae629-r0 do_compile: NOTE: fsbl: compiling from external source tree /home/fpgauser/PetaLinux-2017-4/tools/hsm/data/embeddedsw NOTE: Tasks Summary: Attempted 2675 tasks of which 2660 didn't need to be rerun and all succeeded. Summary: There was 1 WARNING message shown. INFO: Copying Images from deploy to images INFO: Creating images/linux directory NOTE: Failed to copy built images to tftp dir: /var/lib/tftpboot [INFO] successfully built project webtalk failed:PetaLinux statistics:extra lines detected:notsent_nofile! webtalk failed:Failed to get PetaLinux usage statistics!
5. Next, build the Fist Stage Boot Loader.
$petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot INFO: File in BOOT BIN: "/home/fpgauser/develop/zyboz7/Zybo_Petalinux/Zybo-Z7-10-2/images/linux/zynq_fsbl.elf" INFO: File in BOOT BIN: "/home/fpgauser/develop/zyboz7/Zybo_Petalinux/Zybo-Z7-10-2/images/linux/system_wrapper.bit" INFO: File in BOOT BIN: "/home/fpgauser/develop/zyboz7/Zybo_Petalinux/Zybo-Z7-10-2/images/linux/u-boot.elf" INFO: Generating zynq binary package BOOT.BIN... INFO: Binary is ready. WARNING: Unable to access the TFTPBOOT folder /var/lib/tftpboot!!! WARNING: Skip file copy to TFTPBOOT folder!!! webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics!
6. If the build is successfully, Xilinx QEMU can be used to test the build by booting it in emulation mode.
$ petalinux-boot --qemu --kernel INFO: The image provided is a zImage INFO: TCP PORT is free INFO: Starting arm QEMU INFO: qemu-system-aarch64 -M arm-generic-fdt-7series -machine linux=on -serial /dev/null -serial mon:stdio -display none -kernel /home/fpgauser/develop/zyboz7/Zybo_Petalinux/Zybo-Z7-10-2/build/qemu_image.elf -gdb tcp::9000 -dtb /home/fpgauser/develop/zyboz7/Zybo_Petalinux/Zybo-Z7-10-2/images/linux/system.dtb -net nic,vlan=1 -net user,vlan=1,tftp=/var/lib/tftpboot -net nic -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 -device loader,addr=0xf8000140,data=0x00500801,data-len=4 -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 -device loader,addr=0xF8000910,data=0xF,data-len=0x4 Warning: vlan 0 is not connected to host network rom: requested regions overlap (rom bootloader. free=0x00000000003aadb8, addr=0x0000000000000000) Uncompressing Linux... done, booting the kernel. Booting Linux on physical CPU 0x0 Linux version 4.9.0-xilinx-v2017.4 (fpgauser@fpgadev) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #3 SMP PREEMPT Sat Jul 27 11:51:22 PDT 2019 CPU: ARMv7 Processor [410fc090] revision 0 (ARMv7), cr=10c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache OF: fdt:Machine model: Zynq Zybo Z7 Development Board bootconsole [earlycon0] enabled cma: Reserved 128 MiB at 0x38000000 Memory policy: Data cache writealloc percpu: Embedded 14 pages/cpu @ef7cb000 s25932 r8192 d23220 u57344 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260608 Kernel command line: console=ttyPS0,115200 earlyprintk uio_pdrv_genirq.of_id=generic-uio root=/dev/mmcblk0p2 rw rootwait
Load image to SD card
1. Change the Root Filesystem Type to SD using the petalinux-config command.
$ petalinux-config -c rootfs
2. In the System Configurations window, navigate to Image Packaging Configuration and select <Select>.
3. Select Root filesystem type (SD card)
4. For Root filesystem type select SD card; use the arrow keys to move up and down and the space bar to make a selection.
5. Press Select and Exit to the first screen and save the configuration.
6. Edit the system-user.dts file to change the bootargs reflect the SD card boot image.
7. Go back and repeat steps 4 and 5.
8. Format a SD Card with 2 partitions;
Partition 1 - At least 500mb (2GB in this case) FAT format
Partition 2 - At least 3GB (reset of 32GB microSD card in this case) ext4 formatted
$ sudo fdisk /dev/sdb Welcome to fdisk (util-linux 2.23.2). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk /dev/sdb: 32.0 GB, 32010928128 bytes, 62521344 sectors Units = sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disk label type: dos Disk identifier: 0x00000000 Device Boot Start End Blocks Id System /dev/sdb1 * 2048 8390655 4194304 83 Linux /dev/sdb2 8390656 62521343 27065344 83 Linux
9. Create the filesystem on the partitions
$ mkfs.vfat -F 32 -n boot /dev/sdb1 mkfs.fat 3.0.20 (12 Jun 2013) mkfs.fat: warning - lowercase labels might not work properly with DOS or Windows /dev/sdb1: Permission denied
$ sudo mkfs.ext4 -L root /dev/sdb2 mke2fs 1.42.9 (28-Dec-2013) Filesystem label=root OS type: Linux Block size=4096 (log=2) Fragment size=4096 (log=2) Stride=0 blocks, Stripe width=0 blocks 1692432 inodes, 6766336 blocks 338316 blocks (5.00%) reserved for the super user First data block=0 Maximum filesystem blocks=2155872256 207 block groups 32768 blocks per group, 32768 fragments per group 8176 inodes per group Superblock backups stored on blocks: 32768, 98304, 163840, 229376, 294912, 819200, 884736, 1605632, 2654208, 4096000 Allocating group tables: done Writing inode tables: done Creating journal (32768 blocks): done Writing superblocks and filesystem accounting information: done
10. Mount partition 1 and copy the following files to the microSD card.
$ sudo mount /dev/sdb1 /mnt/boot/ $ mount /dev/sdb1 on /mnt/boot type vfat (rw,relatime,fmask=0022,dmask=0022,codepage=437,iocharset=ascii,shortname=mixed,errors=remount-ro) $ sudo cp images/linux/BOOT.BIN /mnt/boot/ $ sudo cp images/linux/image.ub /mnt/boot/ $ ls /mnt/boot/ BOOT.BIN image.ub $ sudo umount /mnt/boot/
11. Copy the image to the microSD card
$ sudo dd if=images/linux/rootfs.ext4 of=/dev/sdb2 347164+0 records in 347164+0 records out 177747968 bytes (178 MB) copied, 539.166 s, 330 kB/s $ sync
NOTE: It may be necessary to run a file system check on the image.
$ sudo e2fsck -f /dev/sdb2 e2fsck 1.42.9 (28-Dec-2013) Pass 1: Checking inodes, blocks, and sizes Pass 2: Checking directory structure Pass 3: Checking directory connectivity Pass 3A: Optimizing directories Pass 4: Checking reference counts Pass 5: Checking group summary information /dev/sdb2: ***** FILE SYSTEM WAS MODIFIED ***** /dev/sdb2: 3757/43472 files (0.6% non-contiguous), 139076/173580 blocks [fpgauser@fpgadev Zybo-Z7-10-2]$ sudo resize2fs /dev/sdb2 resize2fs 1.42.9 (28-Dec-2013) Resizing the filesystem on /dev/sdb2 to 27065344 (1k) blocks. The filesystem on /dev/sdb2 is now 27065344 blocks long.
12. Remove the microSD card from the PC and install it on the Zybo Z7-10.
1. Ensure the Zybo Z7-10 has JP5 set to SD and JP6 set to WALL and the board is powered by a 5v Power Adapter and a USB cable is connect to a computer.
2. Open a serial connect to the Z7-10 and power on the board.
NOTE: minicom was used in this instance.
3. If the boot sequence for the board should appear in the serial connection if the image build was successful.
4. The board will boot to a root user prompt. Standard Linux commands can be used to navigate the filesystem, and if an Ethernet cable is connect, the ip address can be obtained via 'ipconfig -a'.
5. The board is loaded with some default digilent-apps such as pwmdemo. This changes the colors on the RGB LED at led6
6. Other demos can be enabled by running petalinux-config again.
7. Video showing the Petalinux example and pwmdemo running on the Zybo Z7-10.
The Zybo Z7-10 is an excellent started development kit to learn both Embedded Linux as well as FPGA design using the Xilinx Zynq-7000 series SoC processor. The Zybo Z7-10 offers many great features to interact the board with and this RoadTest only scratched the surface of those options. Initially I intended to run the reVISION suite with xfOpenCV and OpenCL on the Zybo Z7-10, but this was designed for more advanced boards and I did not have the time to port the code to fit the Z7-10. This is still planned for future work with the Z7-10 and I have a Autonomous Car in progress to demo this with. During this RoadTest there we several issues seen with running the demo examples from Digilent and much of what is found on the web was of some use but there were cases where there was no resolution. Cases where demos were created in older versions of the Xilinx tools such as 2016.4 or 2018.2 rather than 2018.3 were challenges. For products designed for the Educational arena, one would have hoped to have an easier path to examples especially for those just getting started with FPGA development. However, this also offers the opportunity for students to hone their skills further by having to port up examples to new versions of the Xilinx tools. I am looking forward to doing so.
My next step with the Zybo Z7-10 board is to complete the Autonomous Vehicle with Computer Vision navigation based on the example that is shown on the Digilent page.
I have already 3D printed the parts from the project and started the assembly of the car.
More to come soon.