This thread is for matters related to a register switching Pro theremin under development..
Full details will eventually be published - at this time however most information is of little use to anyone except those having private communication with me.
Block diagram for V0:1 of this theremin -
V0:2 -> Ref oscillator now in PLL using PSoC 500kHz clock as master, PLL error voltage is fed to pitch VFO for thermal compensation.
Original register selector for mixed signal wave-shaper - consumes too many PLD resources:
Improved register selector for mixed signal wave-shaper -
Everything would have worked, except I wrongly assigned the symbol to the old circuit, so thought I was adding the improved version when in fact it was still calling the original!
Fixing this, everything fitted!
Many thanks to Dana and hli at the Cypress forum for their help ! External clock for TCPWM components - Help please!! - Cypress