8 Replies Latest reply on Sep 1, 2017 2:47 AM by rachaelp

    CC430F513* CLEARANCE ERRORS ON EAGLE

    mrrutto

      Hi,

      I'm creating a PCB based on the CC430F5137 chip from Texas Instruments. I've routed all wires and whenever i run DRC I keep getting clearance errors between the smd footprints of the chip. How can i clear this errors?

      ps: The photo is a picture when running the DRC with all clearance settings at 0 mils

        • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
          rachaelp

          Can you post up a picture of the clearance page in the DRC setup?

              • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
                CadSoft Guest

                On 8/30/2017 10:26 AM, Michael Rutto wrote:

                Here is the picture

                 

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                The spacing between pads is less than your DRC allows.

                You can adjust DRC (Bad idea) or approve these errors. (Just pesky)

                 

                Doug

                 

                • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
                  rachaelp

                  I'm not sure what setting the clearances to 0mil on the "different nets" section is. For the same nets section it says it disables the check but it's clearly not doing this in the case of the different nets. I suspect setting 0mils is making EAGLE switch to some default value. As a test set your trace to trace, trace to pad, and pad to pad clearances to 6mil and see if the issue clears up. Looking at your first image 6mils should be less than the gaps you have.

                   

                  HOWEVER! What the DRC should be set to is the manufacturing capability of the manufacturer you plan to use for your PCB. Depending on who you use they may provide an EAGLE .dru file or alternatively you might have to dig through their specs and manually set up the DRC to their capabilities. If once you've done this you still have issues then it may be that you need to choose another manufacturer or speak to them to see if they are ok with a reduced clearance between pads and then either adjust the DRC accordingly (which will apply to the whole board) or approve the DRC errors around this specific IC.

                   

                  Best Regards,

                   

                  Rachael

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              • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
                geralds

                Hi,

                 

                ist seems that your drawings of the component is wrong.

                http://www.ti.com/lit/ds/symlink/cc430f5137.pdf

                 

                clearance settings to 0 would be also wrong, minimum what  the manufacture can do as well.

                Eagle use default about 6mils. Some manufacture can handle about 4mils of clearance.

                 

                hm.. have you some lines or particles on the first layer that are not electrical?

                That would also create an exception error.

                 

                Gerald

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                  • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
                    mrrutto

                    I haven't put anything else close to the CC430 apart from a set of  vias under the thermal pad.

                     

                    Anyway i went back to the datasheet and found out the package i was using, from one of the TI libraries, was wrongly designed. I've since changed the package and now there's no DRC errors regarding to clearance when using 6mils spacing.

                     

                    Thank you.

                     

                    Rutto.

                      • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
                        rachaelp

                        Michael Rutto wrote:

                         

                        Anyway i went back to the datasheet and found out the package i was using, from one of the TI libraries, was wrongly designed.

                        I think here there is a valuable lesson to be learned. Never trust a library you didn't create (or at least thoroughly check) yourself. This is why I don't use the standard libraries at all.

                         

                        Anyway, I'm glad you got to the bottom of the issue and it is now working for you.

                         

                        Best Regards,

                         

                        Rachael

                    • Re: CC430F513* CLEARANCE ERRORS ON EAGLE
                      CadSoft Guest

                      On 30.08.2017 15:31, Michael Rutto wrote:

                      Hi,

                      I'm creating a PCB based on the CC430F5137 chip from Texas Instruments. I've routed all wires and whenever i run DRC I keep getting clearance errors between the smd footprints of the chip. How can i clear this errors?

                      ps: The photo is a picture when running the DRC with all clearance settings at 0 mils

                       

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                      Remember to check clearance on net classes too. (Menu:Edit->Net classes)