Hi Noelia Scotti,
You have to length match all the single ended DDR signal based on the clock signal length.
Differential pairs tolerance should be in +- 5 Mils, Single ended signal tolerance should be in +-20 Mils.
Termination should be placed nearer to the pin.
You ca refer this DDR design guidelines .
Yes, I know the LPDDR3 routing rules but I want to understand the WARP7 design.
Hello! I was analyzing the LPDDR3 routing with the Allegro Free Physical Viewer. I saw weird things... There are strobe lines longer than clock lines, for example strobe0 836 mils and clock 413 mils on the same layer L4. I understand that max strobe length is clock length - 10 mils.
There is one address line with 273 mils and another one with 434 mils on the same layer L2.
I don't understand this, how is it possible?