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I've been surprised how well the training is written and presented.
I've done a fair bit of training material preparation in the past, and it's always a fine balance between satisfying the teaching requirements, reducing the risk of errors and frustration, and recognising that engineers will always go off on their own and ignore the steps occasionally : ) it's just a natural part of being an engineer, to want to explore and learn more, so the trainer anticipates that.
In terms of the technical content, so far there is more on working with the Zynq rather than actual VHDL, but I had a feeling that would be the case since it's not feasible to learn much VHDL at the same time as the massive task of learning how the SoC works and how to use it in Vivado. I think for the Zynq/Minized, we're learning what is needed in an acceptable order so far.
I wouldn't say the course is easy, there are some concepts that have to be just accepted until the user gets further and is in a position to go back to understanding those concepts, but it is manageable with very little prior knowledge needed.
The blogs are taking a while to write, because there is a balance between learning and then reporting what we've been doing, and sharing some aspects of how to do it. It has been very helpful that we're all working on this at the same time with a common goal paced out each week.
I think it will be sufficient for a project.. I've started thinking about what I'd like to do for that, I still need to decide.
In terns of the hardware, the Minized is nice.. I'd like to integrate it into a few projects.
I'm not a trainee but I'm enjoying following along with P2P. Some of the blogs are really helpful and I appreciate all the effort that's being put into them.
I suspect the next module will also not concentrate on the PL itself but will focus on the software side of the PS.
I'm on the last 2 labs in the first module, although I haven't been able to work on them this week so far.
I'll try and finish up this weekend.
I have been down with flu for the last couple of days. I have to also finish the last few labs.
I think this weekend should be time enough to do the tests and prepare the blogs as well.
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I'm on the way to finishing up soon as well. My plan had been to finish the modules this week; but that isn't going to happen at this point; not until next week. At any rate; as a few of us have mentioned, the training is a lot about "how to use Vivado" and not really about the nuts and bolts about how an FPGA works. I don't have any formal experience programming FPGAs so this has been a big learning curve for me (as expected; and it has been fun!). So when they start talking about Verilog, for example, I spend some time researching that and how it works.
I would say that this training assumes that the learner already knows a decent amount about the hardware and this will teach them how Vivado works. It shows things like how to add peripherals like BRAM, import hardware templates and so on, but not a lot of detail on what those items really are; and especially not how & when to use them. There has been almost nil mention of logic gates; which kind of sit at the core of what FPGAs can do.
Can we get more details about the next module? What about the project? I'm ready to order a bunch of stuff to build what I had been planning (a line follower) but wasn't sure if we would be guided towards some more specific type of thing.
And - could we get new dates posted based on the current status?
I've been watching the progress (or lack of progress) of everyone. It looks like at least some of you are ready for the next module. So, I'll starting sending it this week.
As far as your question/comment regarding" not much on logic gates" and "a lot on tool use (Vivado)....."
I went into this project knowing that some of you would have little knowledge of FPGAs and some of you would have had decent knowledge or familiarity of FPGAs. I wanted both types of people; I wanted to see how you handled the training in both cases.
The training does assume you know something about the hardware (FPGA, Soc). But your comment makes me want to ask the question: if someone has an electrical or electronic engineering degree, how much times in your course-major classes were spent on programmable logic devices, by percentage? My next question would be, if you do not have an ee degree, do you have a CS degree? If so, do you feel the course covers enough information such that you can do something (a project) even though you may not know the intricate details of the hardware?
On a separate not, I'd like to respond to your comment on a different level. Full disclaimer: the following is my impression and/or opinion....
Since I have meetings with the sponsor, I am given presentations (which one could consider training though that's not the intent) so I can better understand their direction. This helps me help them create projects. One of the problems of adopting programmable logic design has been the need to know the hardware. This problem has bigger than I even suggest. Software engineers traditionally have been at a disadavantage because hardware has not always been their specialty. Well, this is changing. They are starting to build platforms that have frameworks which contain levels of abstraction and overlays or "wrappers" such that software engineers can do PLD hardware design without intimately knowing the hardware; but tool knowledge would be essential. This field is evolving rapidly and I anticipate that programmable logic hardware design will require less hardware knowledge than in decades past.
-Path to Programmable Program Manager
I have done all laboratories from module one. The module one is very well written and everything is nicely explained. From each laboratory we are able to learn how the SoC works and how to use it to achieve best performance. After this module we have basic knowledge about MiniZed/Zynq and Vivado.
The Speedway Training is great but i felt that tools are very powerful and giving a lot of abstraction of how we implement some designs in a PSoC and i enjoyed working with them.
I would like to ask you if i can post the content about the implementation details of the project i am working on along with the training with this PSoC so that it would give some unique taste to readers .
sure. go ahead.
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PSoC (with that capitalization) is a trade mark of Cypress for their family of micro controllers with a little tiny bit of programmable logic.
It can be very confusing if you use the same term to describe the Zynq which is a different thing altogether.
Thank you Michael for your Correction , I will now onward refer it as Minized itself .
Keep up the good work !
I look forward to seeing more about your project.
To all Path to Programmable Trainees.
I going through all your blogs and they are pretty interesting. I'll be making comments on them in the next couple of days. I see most of you are on track so I wanted to ask you, how's it going? Was this program what you expected? Or something else?
As far as next steps, it looks like some of you are close to ready for the next module. So, I will be sending it out to you in the next week.
Thanks for your efforts.
Path-to-Programmable Program Manager