3 Replies Latest reply on Dec 19, 2017 7:51 AM by npoureh

    Memory Interface Generator on XZ7100?




      We are considering design an accelerator that make use of the Xilinx DDR controller IP so that the PL can access DRAM directly without AXI-DMA; however we just found from the manual that the DDR interface on Zynq MMP is connected to Bank 502, which is only connected to the PS. Is it possible to use the Memory Interface Generator on Zynq MMP XZ7100? Thanks a lot!