6 Replies Latest reply on Jul 10, 2018 2:49 AM by maxmackey

    PJTAG header & ARM debug problems



      We are using MITX board with Linux kernel from Xilinx. Facing issues with linux kernel driver for USB, we are trying to debug it with Segger J-Link base with PJTAG header on the board.

      I set-up DS-5 tools from ARM to work with J-link base. So it show s up as J-link USB in the connections section. When I try to connect to the ARM processor 0 or 1, the error I get is:

      Could not measure total IR len. TDO is constant high.

      The tool is reporting the correct information as I have verified the voltage on the header pins (5,7,9 & 13 for TDO etc..) to be about that.I have tried independent and cascaded modes but no help. Is there any way I can debug the problem?


        • Hello Michael,

          Hello Michael,


          There is a reference design showing how to use the ARM DSTREAM on the Mini-ITX Reference Design page:




          As detailed in the design you do need to program the PL first to connect the PS PJTAG signals to the PJTAG header via EMIO pins if you have not done this step yet.



          • Issue continues

            I added in the recommended PJTAG to EMIO  interface to our bit-stream according the reference design. But the issue still remains..is it because Xilinx Z7100 is not supported by J-Link base? Do we need to get the other expensive tools ? Is U-link Pro  recommended?

            • RE: Issue continues

              Hi Michael,

              First of all, let me state that we cannot provide support for something that have have not tested ourselves and therefore we will not recommend the J-Link or U-Link Pro solutions for your application as we have only tested using DSTREAM.

              That being said, I am not aware of anything that would technically prevent either of those devices from connecting to the Z7100 device on Mini-ITX.

              Keep in mind that the Zynq PS also requires settings to redirect (multiplex) the PJTAG connections to EMIO ports for them to connect to your PL design.  This implies that an FSBL with this PS configuration be used to first configure the MIO (EMIO is implied with this configuration) prior to loading the bitstream.  You can do this from Xilinx SDK also by configuring the PS (ps7_init) and loading PL bitstream from a debug configuration.

              Since you did not mention whether or not you have tried the reference design that Gary pointed out, I would suggest that you do this first.  That reference design provides the FSBL and the bistream within a BOOT.BIN file that can be used to boot your Mini-ITX board with a minimal PS and PL configuration needed to redirect the PJTAG interface to through the PL and provide access to the DAP out to the physical header.  If that example BOOT.BIN file enables your J-Link to connect, then it is simply a matter of identifying the differences between the reference design and the design that you are currently working on in order to add the hooks needed to connect to the DAP.  If the example BOOT.BIN file does not enable your J-Link to connect, then it is more likely a target configuration issue with ARM DS-5 which is addressed differently.

              For the DS-5 target configuration, take a look at the following ARM guide for bringing up new platform configurations:


              In either case, please let us know about the outcome and please be detailed in what you have tried.  Since you are trying something that likely has not been tried before, your knowledge and experience in this will be very helpful to this community.



                • Hi Kevin,

                  Hi Kevin,

                  It is understandable that support is not provided because replicating the issues is harder. Please bear with me as I am new to using FPGA tools & as well as hardware.

                  Anyway, I was successful in utilizing the reference design as is with provided BOOT.bin and getting the J-link basic to recognize the ARM DAP via the PJTAG header. I did not go past that point in terms of actual debugging process after hardware is recognized.

                  My next step was to add this PJTAG feature to our current hardware design. That's where I have issues currently. Our design has a top level module which instantiates a wrapper module, which in turn instantiates the module where PJTAG connectivity to processing_system is port mapped etc. While PJTAG_TDI, TMS & TCK (inputs) show up in the routed design, PJTAG_TDO (output) does not. Synthesis spews warning such as:
                  Net PJTAG_TDO in module wrapper does not have driver.
                  Implementation report says/; "Could not create 'DRIVE' constraint because cell PJTAG_OBUFT_TRUE.jtag_obuft_inst is not directly connected to top level port.
                  So looks like TDO is getting trimmed somewhere in the process causing the problems, though I have verified that all of connectivity in top module, wrapper etc. is intact. Some pointers in this direction will be very helpful.

                  Thank you!

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