No, you would not need to disable any of the devices currently using the MIO banks to route the SPI signals to the PL via EMIO. If you take a look at Figure 2.3 in the Zynq Technical Reference you can see that the EMIO connections to the PS SPI controllers are picked off 'before' they go to the MIO Mux.
You would also have the option to implement an SPI interface in the PL using the AXI_Quad_SPI IP. I have found the AXI SPI controller to have fewer limitations than the PS SPI controllers.
That puts my mind at rest. Appreciate it.
I am going to second Gary's recommendation of using the AXI_QUAD_SPI IP, it is definitely the way to go. There is a lot more flexibility that the PL SPI controller offers.
We are currently using the MicroZed board and are looking at the MMP for a new project.
Looking at the Schematic, there are no SPI ports broken out to the connectors as they are on the MicroZed. I understand that the SPI lines can be routed through the EMIO, but looking at the technical reference manual for the Zynq, bank 500 and 501 are already dedicated as QSPI, Ethernet, USB, etc.
Would I need to disable (for example) the QSPI Flash memory to use an SPI port routed through the EMIO, or do they coexist?