Won’t that just silence the warning and tie those pins off? I actually need to connect those pins to use the PCIe block.
Whoops, they're under an interface pcie_7x_mgt :)
I've experimented with the PCIe PIO sample project and now I'm trying to create my own from scratch with IP Integrator but I'm having trouble figuring out how to connect the actual PCIe signals pci_exp_txn/txp/rxn/rxp.
This is what I've done for a simple test case:
1. Create a new Vivado project
2. Select the PZ 7015 + FMC2 board configuration
3. Add the 3 constraint files from the sample project + PCIe IP (fmc2_io.xdc, vstd_3p3.xdc and xilinx_pcie_7x_ep_x1g1.xdc)
4. Create a new block design in IP Integrator as follows:
a. Add Zynq PS and run block automation
b. Add 7 Series Endpoint Block for PCI Express
c. Connect FCLK_CLK0 to M_AXI_GP0_ACLK and sys_clk on the PCIe block
d. Pretend the AXI-S interfaces are connected to something else as I have done this, but it's not important for this example
Now validate design.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
I cannot see these pins anywhere in the Board, Signals, Design tabs, or in the PCIe block in IP Integrator. How do I connect them? Do I need to add them to the constraints files?