4 Replies Latest reply on Jan 11, 2017 9:03 AM by pdaderko

    SuperSequencer not working with PWR_ENABLE pin

    pdaderko

      Hey,

       

      I'm having a problem with my PicoZed SDR SOM not booting up when I control the power via the PWR_ENABLE pin.  According to the manual, the ADM1166 won't enable supplies until PWR_ENABLE goes high, but looking at the schematics and sequencer state machine, it doesn't appear to be the case.

       

      The PWR_ENABLE pin controls the enable line to the 1.0V (VX2) and 0.95V supplies (VX1).  The state machine goes to state 3 once JX_VIN (VH) is OK.  State 3 enables VIN and goes to state 4 after 400ms.  State 4 expects that the 0.95V (VX1) supply will be up, otherwise goes to the failed state forever.  But, with PWR_ENABLE low, 0.95V will not be enabled when it gets to state 4.  Rather than waiting for 0.95V to come up (like the manual implies), it fails.

       

      Any chance of an official update for this?  While I can try to set up my own custom sequence, I'm slightly hesitant because I'm sure there are a bunch of minor details that you don't find out are important until you screw them up. ;-)

       

      Also, if the PWR_ENABLE pin could work to turn off power when the module is not needed, and then back on when needed again, this would be ideal (rather than going to the failed state forever any time PWR_ENABLE is low).  Since the pin actually only controls the 0.95V and 1.0V supplies, is there any danger of damage by removing these supplies while running?  I assume there's some delay before the sequencer notices, and powers everything else down.

       

      For my application, using PWR_ENABLE as a SOM on/off switch would be very useful, as it's battery powered, and may go for long periods of time where the PicoZed SDR isn't needed.  Unfortunately, I didn't put a FET on my carrier to switch VIN on/off, as I planned to use the PWR_ENABLE pin for that function.

       

      Thanks,

      Pat

        • Hi Pat,
          mbrown

          Hi Pat,

          I see the problem exactly and I'm investigating with the designers, but with the holidays coming up things are a slower. I'll get back to you ASAP.

          (You're right that changes to the sequencer should not be taking lightly)

           

          /Matt

          • Yep, I understand things go
            pdaderko

            Yep, I understand things go slower around the holidays... just now getting back to it myself.  Please let me know once a solution is available, though for the time being, it's not holding up my development, as I can just always leave it enabled while powered in the lab.

             

            Thanks,

            Pat

            • We confirmed that using PWR
              mbrown

              We confirmed that using PWR_ENABLE as an On/Off signal is completely safe. The power down sequence we have in the ADM1166 state machine ensures that rails are powered down in the correct order to avoid any device reliability issues. The only issue you'll have is that our state machine can only be reset by a power cycle to the SOM. This is by design. Here's why...

               

              If a voltage regulator catastrophically fails, causing the ADM1166 to shut down the SOM, we don't want the SOM to perpetually reboot, shutdown, reboot, shutdown. The idea is that the ADM1166 logs the fault condition and keeps the module powered down to protect the system. In our state machine, the shut down sequence ends in a state that toggles PG_MODULE. On Rev E SOMs this will toggle the PG_MODULE LED as a visual indicator that the ADM1166 observed a problem and shut things down.

               

              I'll update the User Guide to include these details. Sorry that it was not explained correctly there.

               

              Pat - I'll contact you via PM to help with customizing the ADM1166 to do what you want so that your custom carrier is usable as you intended.

               

              A few more details for the hardware-minded and the curious...

              The ADM1166 does not monitor PWR_ENABLE directly. However, it does monitor 0.95V (Zynq Vccint) and 1.0V (Zynq Vccpint). The regulator that creates them does use PWR_ENABLE as an enable. Therefore, pulling PWR_ENABLE low disables those voltages, the ADM1166 observes a UV condition on them as they collapse, and enters it's shutdown sequence. Is this safe for Zynq? Yes.

              Xilinx DS191 for Zynq confirms:

              Page 9:

              ===> No issue for us. Vcco_MIO0/1 and Vccpaux are all connected to 1.8V.

              Page 9:

              ===> No issue in this scenario. If 0.95V (Vccint) and 1.0V (Vccpint) both collapse, the requirement above is still maintained. Our ADM1166 state machine power down sequence ensures that the I/O voltages (Vcco) are disabled before Vccaux.

               

              Page 10:

              /Matt

              • >Pat - I'll contact you via
                pdaderko

                >Pat - I'll contact you via PM to help with customizing the ADM1166 to do what you want so that your custom carrier is usable as you intended.

                 

                I tested the solution that Matt provided, and it worked great.  Thanks again for the help!

                 

                Pat