My suggestiong would be for you to ask your question over at the Xilinx forum as they are the ones who generated that material you are referng to and would be best suited in assiting and debugging the reference design
Thanks Josh, I'll do that and any response I get I'll post back here as well.
I'm a new user to SDSoC with good experience of embedded programming (C, C++) and some FPGA experience.
I have a new zedboard and I want to experiment with the Xilinx reference code for Lucas-Kanade Optical Flow. (per XAPP1300, Feb/3/2017 from Xilinx).
I've downloaded the code and successfully built a bitstream and SD card for the zed from SDSoC with release config = Release. Everything works correctly on the board.
However, whenever I try a release config=Debug, I always get the preprocessor error (as extracted from the log file):
In file included from /home/alan/VisionProject/LK.Ref.App.ZYBO/src/LKof_defines.h:139:
In file included from /opt/Xilinx/SDx/2016.4/include/ap_int.h:30:
/opt/Xilinx/SDx/2016.4/include/etc/ap_int_sim.h:25:2: error: ap_int simulation header file is not applicable for synthesis
#error ap_int simulation header file is not applicable for synthesis
I would not expect that error, as everything synthesised correctly for the release config.
Has anyone had this problem or know how to help. I'm short on time available for a project and would appreciate any assistance.