Hello I'm using a ZYNQ Zedboard development board. I'm studying the Partial Reconfiguration using ICAP. I implemented a system with Zynq Processing Unit, ICAP and AXI DMA. The DMA accesses to the memory and transfers the partial bitstream from DDR3 to ICAP using 32 bit AXI stream. Using a Clock Wizard peripheral I examined the frequency behavior of the system and I got that the transfer time from ICAP to reconfigurable partition decreases linearly up to 200 MHz, beyond this frequency there is a saturation and the time doesn't decrease with increasing frequency. I found on the AXI DMA datasheet that maximum frequency using AXI stream for ZYNQ device is 200 MHz. My question is how does the DMA receiving a clock input greater than 200 MHz to work anyway to 200 MHz? DMA uses an interna FIFO and performs an input clock domain control?