We have not. My ssuggestion would be to revert to Vivado 2014.4
Vivado 2016.3The HDMI reference design is running the VDMA engine and the Video stream comes all the way to the Video-Stream to Video converter IP block. The problem is: VTC, the video timing generator is not generating the v-sync and h-sync. I'm looking into the VTC control register setup now to see if the generator is enabled and detector is disabled. So far it is. The VTC control Register 0 (XVTC_CTL) is configured as: 0x03f73f06. I don't know why the h-sync and v-sync are not being generated. Any ideas?
Hi I am trying to use the ZedBoard_HDMI_Display_Tutorial_2013_4_20140623.zip that I downloaded from Zedboard reference design forum at:
ZedBoard HDMI VIPP, Vivado 2014.
I have a Vivado 2016.3 version and theTCL files are outdated. Has anyone build this design in Vivado 2016.3 version