The VCCAUX_IO is used for the PL HP banks and can be set to 1.8V or 2.0V. We set/drive the VCCAUX_IO with 2.0V on the MMP BB2 to allow customers to run the HP IO as fast as possible. If you are can live with slower data rates, feel free to set the VCCAUX_IO to 1.8V. DS191 and UG471 describe the relationship between the VCCAUX_IO value and the supported data rates.
But how can the user use HP IO at all? If I understand the documentation correctly, only HR banks are routed to User I/O, therefore only the DDR3 interface and the Flash interface is using VCCAUX_IO. And for the DDR3 at 1066, 1.8V is sufficient. Or am I missing something here?
The VCCAUX_IO rail on the MMP BB2 was implemented to support other MMP families such as the K7 MMP. In the case of Zynq MMP, the VCCAUX_IO is not used at all. The DDR3 on the Zynq MMP is PS DDR3 (not PL) and it does not use the VCCAUX_IO voltage rail. If your baseboard is designed to work with Zynq MMP only, then the VCCAUX_IO can be connected to 1.8V or 2.0V.
I'm designing my own baseboard for an Zynq MMP (AES-MMP-7Z045-G).
Now I'm wondering, why the documentation for the MMP as well as for the BB2 use 2.0V as VCCAUX_IO. When implementing the reference design in Vivado using the board definition files "AES-MMP-7Z045-G-Board_Definition_Files_Vivado_2015_3_v1" provided by Avnet, the design prescribes 1.8V for VCCAUX_IO in the "Power Supply Summary"
From the documentation of the Zynq 7045 I also cannot find why 2.0V should be applied here, as the DDR3 runs with only 533 MHz, which is supported with 1.8V if I read Table 53 in DS191 correctly.
Therefore, I would think I should apply 1.8V to JX1-116?
Any comment or explanation is highly appreciated.