20 Replies Latest reply on Jan 9, 2019 3:19 AM by Sparkylabs

    More bugs

    Sparkylabs

      1) If I go to edit my board shape I get put into some undefined mode where I cannot edit it or get out of it. The back button will undo things I have done whilst keeping me in a greyed out - out of control mode. The only way out is to close without saving and loose any changes not saved before entering the attempt to change board outline mode. I am also still confused as to why the outline needs defining twice! because unless I put a line around the board shape the autorouter gets confused and so does the PCB manufacturer! The board shape should define the outline in the Gerber. I can send an example project in.

       

      2) Via's: I want to place a series of via's on my board. This board has several layers of different nets. I want my via's to be GND nets. I am constantly asked if I want to repour my plane, if I say yes this means that the plane has to be regenerated for every via I place and will take forever. if I say make unpoured then the via defaults to another net regardless of my setting. I guess I will have unpour all of my polygons and hope for the best! but really this all needs sorting out to make it easier. We have been through this before and demonstrated that things do not behave logically.

        • Re: More bugs
          Sparkylabs

          Update 2) when I place a via with no poured planes I choose one net but this keeps changing. I have to manually edit dozens of vias!!!!! what a hopeless bunch of idiots that wrote this program. It won't even follow SPECIFIC user input. !!!

          • Re: More bugs
            Sparkylabs

            3) dragging tabs around does not even work although appears to be supposed to be possible

              • Re: More bugs
                e14softwareuk

                1) It is normal to need three board outlines for a design

                1. Board definition (as seen in 3D view)
                2. Gerber board outline on the Outline layer
                3. Copy of board outline on the global Keepout Layer

                In general it can be easier to use the option to define board outline (3D view) by selecting an existing set of primitives (e.g. the gerber outline) and using the option to define from primitives.

                 

                2) If your polygons are unpoured (typically the easiest way to work on a board) you can place several vias with a given net. Start the via command, hit TAB and define the net and then place on to the board. All the vias should keep the same net until you are done. Don't try to copy and paste vias as this does revert the net to unconnected.

                  • Re: More bugs
                    Sparkylabs

                    OK I will have a go with the board outline from the board edge line. I don't understand, a board edge is the same in the gerber, in the 3D model and as a default keep out area or better put a keep in area not that CS abides by it. This is a joke! what sane person does not have these three elements the same?

                     

                    2) DOES NOT WORK, THE VIA CHANGES OF IT'S OWN ACCORD BECAUSE CIRCUIT STUDIO IS BUGGY!!!! the only way out is to place via's not on the board and then move them which is a silly work around for buggy software!

                • Re: More bugs
                  Sparkylabs

                  A further bug. If I have a polygon pour in a solder paste layer assigned to a net it also covers other nets in what will be a massive short circuit!

                    • Re: More bugs
                      voltsandjolts

                      nonsense input = nonsense output

                        • Re: More bugs
                          Sparkylabs

                          You mean the options I am being given are a nonsense? If a net can be assigned it follows that only that net will be covered.

                            • Re: More bugs
                              voltsandjolts

                              It appears that CS design rules are not applied to polygons on non-copper layers, they are not even assigned to a polygon class when on a non-copper layer. So, no, they won't work on the solder paste layer.

                               

                              However, it's very unusual to have large areas of solder paste that might be generated with polygons on the paste layer. If you are fixing a large (perhaps mechanical) component to the PCB by using a large area of solder paste there is a risk of shorting nearby nets due to the volume of solder which can be squeezed out during component placement. Normally you would use a sparse pattern of small paste squares to fix on larger areas.

                               

                              Paste mask is a whole science with some detail covered in IPC-7525 but this has a good introduction:

                              http://www.jps-pcb.com/upfile/2017/02/20170216155446_850.pdf

                              Page 27 illustrates my point but it's worth skim reading from page 10.

                               

                              If you say this is a bug in CS, I would say the bug is allowing polygons on the paste layers.

                        • Re: More bugs

                          If I have a polygon pour in a solder paste layer assigned to a net it also covers other nets in what will be a massive short circuit!

                          Plex Lucky Patcher Kodi

                            • Re: More bugs
                              e14softwareuk

                              As already discussed polygons on non-electrical layers do not operate as normal polygons - they don't clear other objects. Ideally CS should prevent the drawing of polygons on these non-electrical layers to prevent confusion. Why are you trying to assign a net to an object on the solder paste layer?

                                • Re: More bugs
                                  Sparkylabs

                                  I'm trying to "uncover" the entire polygon so that it gets a coating of solder paste. The easiest way to do this is duplicate that layer and tell CS that it belongs to that net assuming that doing so would mean that it would follow the same rules and go around any obstacles in the same way the original polygon did. It's not a problem in this design as there is very little to miss but I would have assumed it would follow the same rules.

                                   

                                  why should I not be able to draw a polygon on a non electrical layer? what is the point of non electrical layer if I can't do stuff on it. I am sorry but as usual we are choosing the lesser of what could be an issue in order to dismiss it. If i want a specific area of copper not covered in solder mask how else do I do it?