3 Replies Latest reply on Feb 7, 2019 3:16 PM by cpdutrow

    PicoZed Power Sequence Sanity Check

    cpdutrow

      Hello,

       

      We are in the process of designing a carrier card for our PicoZeds and I wanted to get a sanity check on our setup for powerup. While we think we are correct, we have another product with a larger Zynq chip that is blowing eFUZEs, so we want to make sure that our setup for this project is sound. It looks like the critical power sequencing is handled by circuitry on the PicoZed itself, but again, would like to verify. For reference, we are using the part, AES-Z7PZ-7Z010-SOM-I-G.

       

      Our plan is as follows...

       

      1. PWR_ENABLE will remain disconnected on our carrier, allowing it to float. Which should allow PWR_ENABLE to pull high to VIN.

      2. VCCO_34 and VCCO_35 are going to be powered up immediately. Although recommend, it appears that it is not necessary for them to enable after the 1.8V (VCCIO_EN) has been enabled? Can these VCCOs come up at any time without adverse effects?

      3. The carrier design guide for the PicoZed suggests that for power down, VCCIO_EN should be pulled low first before PWR_ENABLE. Is this something that our carrier needs to handle, or is it handled by the PicoZed itself?

       

      Thanks for your assistance,

      Chris

        • Re: PicoZed Power Sequence Sanity Check
          ctammann

          Hey Chris,

          So the enable for the SOM sounds good. However, you need to gate your Vcco supplies off of the 1.8V PGOOD (Vccio_en). The reason being the core has to come up before aux, and aux before the bank voltages. If you power up your carrier provided bank voltages at the same time as the SOM input power you will be violating that sequencing.

           

          For power down sequencing, it is ok to shut down all power at the same time. If you have your vcco banks enabled by VCCIO_EN, then if you powered down the SOM it would power down the banks as well (pgood from the 1.8V supply would go low). The key is that you don't want to supply any voltage to the SOM if the SOM isn't already powered. Also be careful about driving I/O signals if the SOM isn't powered up. Let me know if that makes sense or if you have any other questions.

          Thanks

          Chris

            • Re: PicoZed Power Sequence Sanity Check
              cpdutrow

              Hi Chris,

               

              Thanks for the response. In regards to enabling the VCCO_34 and VCCO_35 off of VCCIO_EN, is there any limit to how late VCCO_34 and VCCO_35 can come up? Is the requirement just a "must come up after the 1.8V but all else is fair game?" For example, lets say that VCCO_34/35 come up 100ms after VCCIO_EN is asserted (and well past PG_MODULE). Will that affect the Zynq's ability to boot? Or any of the peripherals? Correct me on this if I am wrong, but I think we should be ok since the Zynq Peripherals (UART, Ethernet, SD card, and QSPI) are on banks separate from VCCO_34/35.

               

              Thanks,

              Chris D.

                • Re: PicoZed Power Sequence Sanity Check
                  ctammann

                  No issue there at all... with the caveat that you don't want voltages on the I/O pins of a bank if the Vcco of that bank isn't powered. As far as the supply sequencing you are correct, once Vccint and Vccaux are powered up you can power up the banks whenever you want. The Zynq boot only needs the core (Vccint for logic Vccpint for processor) and auxiliary (Vccaux for logic and Vccpaux for processor) voltages to boot. PicoZed combines the PS and PL domains (same 1V supply for the core and same 1.8V supply for aux).

                   

                  I just wanted to add that caveat because if you are driving the I/Os on an unpowered bank they can backfeed and cause damage.