30 Replies Latest reply on Sep 6, 2019 11:25 AM by drozwood90

    No Ultrazed-EG SDSoC platform supplied

    oseya

      There is no SDSoC platform available from Avnet for the Ultrazed-EG board

      In the reference design page Zedboard

      The SDSoC platform v2018.2 contains a corrupt platform for the Ultrazed-EG board (you can check it yourself it's even obvious in the pdf)

      The SDSoC platform v2017.2 link is broken https://avnet.egnyte.com/dl/FxDY3zWXMQ

      If anyone still has the platform files would you mind posting it online

        • Re: No Ultrazed-EG SDSoC platform supplied
          drozwood90

          Hi there,

           

          Are you trying to get the platforms for the UltraZed-EG with IOCC?

          I used the link you provided to access the Zedboard.org website.  Then downloaded every SDSoC file (including the whitepapers).  I do not experience what you say regarding corruption, nor broken links.

          I am not sure where the egnyte link you are using came from, but all the files listed on the Zedboard.org link you provided worked for me.

           

          Perhaps your browser didn't download properly?  I used Chrome and FIrefox to download the 4 files listed on the webpage you linked.  Each unzipped without issue.

           

          Please help me to help you, let me know which platform in particular you are trying to download, which browser you are using as well as which Zip you are trying to get.  The filename of the zip file would be most helpful.

           

          I'm also not sure what you mean that "it's even obvious in the pdf".  I took a look in the PDF and do not see any wording regarding corruption.

           

          --Dan

            • Re: No Ultrazed-EG SDSoC platform supplied
              oseya

              Hello Dan,

               

              yes I am using Ultrazed-EG IOCC board,

               

              for the 2017.2 SDSoC platform the archive you downloaded just contains the pdf guide, inside of the pdf you will find the link to download the SDSoC platform so that you can use it yourself, but this link is broken.

               

               

              for the 2018.2 platform look at the pdf page 15, I put a screenshot, for the uzefiocc_avnet board....the location and board type are set wrongly...which leads any attempt to building an application project on this platform not to compile

               

              thanks for your help

                • Re: No Ultrazed-EG SDSoC platform supplied
                  drozwood90

                  Hi there,

                   

                  I see what you mean now, thank you for being specific.  It is really helpful to get to a resolution quickly!

                   

                  I believe the 2017 file was removed due to obsolescence issues with the older tools.  I am sorry the file was not updated.

                  As for the 2018 file, the pin map for the two platforms should really be the same - from the standpoint of the SOM.  The Matrix Multiply example that was provided was actually compiled with that platform.  The prebuilt boot.bin file was included.  I have personally booted the boot.bin in the folder for the IOCC, on my IOCC without issue.

                   

                  Regardless, this should not prevent the build from compiling, just possibly not having the correct pin in the correct place, although I do not think that would be an issue to start your design efforts - especially considering the portability of the SDSoC design structure.

                   

                  While I check on the naming issue and see if there is a new version coming soon for the 2018.3 tools, can you tell me if you installed the board definition files?  That would prevent the compilations.  In the mean time, I would start out with the platforms as you have them and as soon as I have something I will update you.

                   

                  --Dan

              • Re: No Ultrazed-EG SDSoC platform supplied
                drozwood90

                Abdul,

                 

                So it seems we had two things going on here.  First the Board name that you pointed out above was not matching is a textual string.  It really didn't matter regarding building or using that.  Second, the platform that you were using WAS actually built incorrectly.  The history I was able to pull suggests that the build flow was accidentally ticked with the PCIe CC board for each.  The new platform that I am making does NOT have this and has the text corrected.  Please note that the OTHER platforms listed all have "AV" as the board name.

                 

                I think the build issue you had, was actually what we spoke about above.  With the platform clamoring for the PCIeCC (when choosing the IOCC), that is what caused you build issues.  It was likely never caught as we install ALL the board definitions on our systems here...and testing the image, it would still boot as both SOM are the same in BOTH cases.  You only target different IO when it comes differences.  Looking at the board presets, I am also seeing differences related to the transceivers, however, again, we are only using a Matrix Multiply to test - so again, we did not catch this really odd mistake.

                 

                Anyway, I've posted all the new platforms for v2018.3.

                http://zedboard.org/support/design/17596/131

                 

                Thank you for bringing the bad one to our attention.  I'll see about correcting the bad file.

                 

                --Dan

                  • Re: No Ultrazed-EG SDSoC platform supplied
                    pmousoul

                    The 2018.3 SDSoC platform says that is only for standalone configuration and not for Linux.

                    Could you please supply a Linux platform configuration for SDSoC?

                     

                     

                    Thank you,

                    Panos

                      • Re: No Ultrazed-EG SDSoC platform supplied
                        drozwood90

                        Hello,

                         

                        I'm sorry, I cannot provide that.  We do not have a BSP for the 2018.3 version at this time.  That is a requirement for this.

                         

                        --Dan

                          • Re: No Ultrazed-EG SDSoC platform supplied
                            pmousoul

                            Hello,

                             

                            do you have a BSP for an older version so I can use the board with SDSoC and linux (not standalone) configuration?

                             

                            Cheers,

                            Panos

                                • Re: No Ultrazed-EG SDSoC platform supplied
                                  pmousoul

                                  So, can I use the PetaLinux BSP in SDSoC and use it as SDSoC Platform?

                                    • Re: No Ultrazed-EG SDSoC platform supplied
                                      drozwood90

                                      You need to modify the BSP to be SDSoC compatible. Check out UG1146.

                                       

                                      --Dan

                                        • Re: No Ultrazed-EG SDSoC platform supplied
                                          pmousoul

                                          Thank you Dan,

                                          I'll try your suggestion and report back.

                                           

                                          Please remove the following links from the ultrazed download page because they can't be used since they depend on a non-existent SDSoC 2017.2 platform!
                                          UltraZed EG SDSoC Platform: UZ3EG_IOCC_DP_SDSoC_2017_2_01_0.zip

                                          SDSoC C-Callable FFT IP White Paper: SDSoC_fft_c-callable_whitepaper-v2018.2-1.zip (maybe also SDSoC_fft_c-callable_whitepaper-v2017.4.zip)

                                           

                                          Cheers,

                                          Panos

                                            • Re: No Ultrazed-EG SDSoC platform supplied
                                              pmousoul

                                              Hello again Dan,

                                               

                                              I tried the following using SDSoC 2018.2:
                                              https://www.hackster.io/anujvaishnav20/building-custom-sdsoc-platform-with-petalinux-268bfd

                                              which uses the steps from:

                                              https://github.com/Xilinx/SDSoC-Tutorials/blob/master/platform-creation-tutorial/README.md

                                              and ug1146.

                                              I used the 2018.2 BSP for the PetaLinux steps:

                                              http://www.ultrazed.org/sites/default/files/design/uz3eg_iocc_sd_oob_2018_2.zip

                                               

                                              But unfortunately it did not work! When SDSoC is calling Vivado to build the bitstream I get an error related to some project files missing..

                                               

                                              I would also like to report that I tested the standalone SDSoC platform provided from:

                                              http://www.ultrazed.org/sites/default/files/design/SDSoC_Platform_v2018p2rev3p2_1.zip

                                              importing the following in the SDx Vivado tool:

                                              http://www.ultrazed.org/sites/default/files/documentations/UltraZed_Board_Definition_Files_v2017_2_Release_All_CC_5_0.zi…

                                              in order for Vivado to build the bitstream when called in SDSoC.

                                               

                                              Unfortunately, the results are:

                                              Calling VPL

                                               

                                              ****** vpl v2018.2 (64-bit)

                                                **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018

                                                  ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

                                               

                                              Attempting to get a license: ap_opencl

                                              WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found.

                                              Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".

                                              Attempting to get a license: ap_sdsoc

                                              Feature available: ap_sdsoc

                                              INFO: [VPL 60-895]   Target platform: /mnt/terabyte/pmousoul_data/Downloads/SDSoC_Platform_v2018p2rev3p2_1/Platforms/uzegiocc_avnet/uzegiocc_avnet.xpfm

                                              INFO: [VPL 60-423]   Target device: uzegiocc_avnet

                                              INFO: [VPL 60-1032] Extracting DSA to /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0/vivado/.local/dsa

                                              INFO: [VPL 60-251]   Hardware accelerator integration...

                                              Creating Vivado project and starting FPGA synthesis.

                                               

                                              WARNING: [VPL 60-1142] Unabled to read data from '/mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0/vivado/output/generated_reports.log', generated reports will not be copied.

                                               

                                              ===>The following messages were generated while  creating FPGA bitstream. Log file:/mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0/vivado/vivado.log :

                                              ERROR: [VPL 49-71] The board_part definition was not found for em.avnet.com:ultrazed_eg_pciecc_production:part0:1.1. The project's board_part property was not set, but the project's part property was set to xczu3eg-sfva625-1-i. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

                                              ERROR: [VPL 60-773] In '/mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0/vivado/vivado.log', caught Tcl error:  ERROR: [Board 49-71] The board_part definition was not found for em.avnet.com:ultrazed_eg_pciecc_production:part0:1.1. The project's board_part property was not set, but the project's part property was set to xczu3eg-sfva625-1-i. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

                                              ERROR: [VPL 60-704] Integration error, problem rebuilding project prj

                                              ERROR: [VPL 60-806] Failed to finish platform linker

                                              ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/mnt/terabyte/pmousoul_data/sw/Xilinx_SDx/SDx/2018.2/bin/vpl   --iprepo /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/iprepo/repo  --iprepo /mnt/terabyte/pmousoul_data/sw/Xilinx_SDx/SDx/2018.2/data/ip/xilinx  --platform /mnt/terabyte/pmousoul_data/Downloads/SDSoC_Platform_v2018p2rev3p2_1/Platforms/uzegiocc_avnet/uzegiocc_avnet.xpfm  --temp_dir /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0  --output_dir /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0/vpl  --input_file /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels vadd_accel:adapter --webtalk_flag SDSoC  --remote_ip_cache /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/ip_cache --xp "param:compiler.deleteDefaultReportConfigs=false" '

                                              make: *** [testme.elf] Error 1

                                              sds++ log file saved as /mnt/terabyte/pmousoul_data/projects/sdsoc_2018.2/testme/Release/_sds/reports/sds.log

                                              ERROR: [SdsCompiler 83-5004] Build failed

                                               

                                              makefile:45: recipe for target 'testme.elf' failed

                                               

                                               

                                               

                                              So, in short I can't use the uz3eg_iocc board even in standalone mode.

                                               

                                              Could you please provide me some help to make this board usable in SDSoC and more precisely how to produce a Linux SDSoC platform for this board?

                                               

                                               

                                              Thank you for your time,

                                              Panos

                                                • Re: No Ultrazed-EG SDSoC platform supplied
                                                  jafoste4

                                                  Hi Panos,

                                                   

                                                  Did you install the board definition files under the vivado install of the SDx install? Based on the first error, that is your problem.

                                                   

                                                  -Josh

                                                    • Re: No Ultrazed-EG SDSoC platform supplied
                                                      pmousoul

                                                      Hello Josh,

                                                       

                                                      as I noted above your post, I did:

                                                       

                                                      "

                                                      I would also like to report that I tested the standalone SDSoC platform provided from:

                                                      http://www.ultrazed.org/sites/default/files/design/SDSoC_Platform_v2018p2rev3p2_1.zip

                                                      importing the following in the SDx Vivado tool:

                                                      http://www.ultrazed.org/sites/default/files/documentations/UltraZed_Board_Definition_Files_v2017_2_Release_All_CC_5_0.zi…

                                                      in order for Vivado to build the bitstream when called in SDSoC.

                                                      "

                                                       

                                                      I believe that the "problem" is that the 2017.2 board definition files imported in Vivado SDx 2018.2 are old !

                                                       

                                                      The standalone SDSoC 2018.2 platform files are stating that the board part name is em.avnet.com:ultrazed_eg_pciecc_production:part0:1.1

                                                      but the 2017.2 board definition files define the following boards:

                                                      em.avnet.com:ultrazed_eg_iocc_production:part0:1.0

                                                      em.avnet.com:ultrazed_eg_pciecc_production:part0:1.0

                                                       

                                                      which as you may notice are not the same !

                                                       

                                                      But, in any case I need a Linux SDSoC platform for this board.

                                                      There used to be one Linux SDSoC platform for the 2017.2 SDSoC in the download files; I've used it successfully in the past !

                                                      But now, unfortunately, there is no Linux SDSoC platform support; I tried to do it myself following the steps described by Xilinx, but it did not work.

                                                       

                                                       

                                                      Cheers,

                                                      Panos

                                                        • Re: No Ultrazed-EG SDSoC platform supplied
                                                          jafoste4

                                                          Hi,


                                                          Yes, the outdated board definition file would cause that issue. Please follow this document to get the latest revision controlled BDF.

                                                          -Josh

                                                           

                                                          http://zedboard.org/sites/default/files/documentations/Installing-Board-Definition-Files_v1_0.pdf

                                                            • Re: No Ultrazed-EG SDSoC platform supplied
                                                              pmousoul

                                                              Hello Josh,

                                                               

                                                              I'm sorry to disappoint you (or me!) but this github repo says it supports up to "Xilinx Vivado Design Suite: Vivado 2017.4" which is old.. and the ultrazed BDF last updated 2 years ago..

                                                               

                                                              If you could find the 2018.2 SDSoC Linux platform files it would be very helpful to me.

                                                               

                                                              I've spend a few days now trying to find a solution following any possible path; I don't want to spent any more time trying things that will not get me to have an SDSoC 2018.2 Linux platform for the ultrazed_3eg_iocc board.

                                                               

                                                               

                                                              Thank you for your time,

                                                              Panos

                                                                • Re: No Ultrazed-EG SDSoC platform supplied
                                                                  fasih.ahmed

                                                                  Hello Panos,

                                                                  Did you find any solution to this problem? I am doing exactly what you were doing and facing the same issues

                                                                   

                                                                  I am using Xilinx Sdx 2018.2 with Avnet UltraZed-EG IO Carrier Card

                                                                   

                                                                   

                                                                  ===>The following messages were generated while creating FPGA bitstream. Log file:/home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/p0/vivado/vivado.log :

                                                                  ERROR: [VPL 49-71] The board_part definition was not found for em.avnet.com:ultrazed_eg_pciecc_production:part0:1.1. The project's board_part property was not set, but the project's part property was set to xczu3eg-sfva625-1-i. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

                                                                  ERROR: [VPL 60-773] In '/home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/p0/vivado/vivado.log', caught Tcl error:  ERROR: [Board 49-71] The board_part definition was not found for em.avnet.com:ultrazed_eg_pciecc_production:part0:1.1. The project's board_part property was not set, but the project's part property was set to xczu3eg-sfva625-1-i. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

                                                                  ERROR: [VPL 60-704] Integration error, problem rebuilding project prj

                                                                  ERROR: [VPL 60-806] Failed to finish platform linker

                                                                  ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/ahmed/Xilinx2018.2/SDx/2018.2/bin/vpl   --iprepo /home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/iprepo/repo  --iprepo /home/ahmed/Xilinx2018.2/SDx/2018.2/data/ip/xilinx  --platform /home/ahmed/Xilinx2018.2/SDx/2018.2/platforms/uzegpcie_avnet/uzegpcie_avnet.xpfm  --temp_dir /home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/p0  --output_dir /home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/p0/vpl  --input_file /home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels mmult_accel:adapter --webtalk_flag SDSoC  --remote_ip_cache /home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/ip_cache --xp "param:compiler.deleteDefaultReportConfigs=false" '

                                                                  sds++ log file saved as /home/ahmed/Xilinx2018.2/SDx/2018.2/workspace-2018.2/MM-test/Debug/_sds/reports/sds.log

                                                                  ERROR: [SdsCompiler 83-5004] Build failed

                                                                   

                                                                  make: *** [MM-test.elf] Error 1

                                                                   

                                                                  10:56:48 Build Finished (took 2m:36s.366ms)

                                                                  @josh do you have a solution to this problem, please let me know

                                                                   

                                                                  Best Regards,

                                                                   

                                                                  Ahmed

                                                                    • Re: No Ultrazed-EG SDSoC platform supplied
                                                                      jafoste4

                                                                      Hi Ahmed,

                                                                       

                                                                      Did you install the board definition file? It looks like its looking for the version 1.1 of the BDF which if you follow the guide above that i posted it should assist you in installing it.

                                                                       

                                                                      -Josh

                                                                        • Re: No Ultrazed-EG SDSoC platform supplied
                                                                          fasih.ahmed

                                                                          Hi Josh,

                                                                          yes, I have installed it from the above guidance but does not work, now I am trying with other board its also not working seems something else :/

                                                                           

                                                                          **************************************************************************************************************************************************************************************************************************************************************************

                                                                          ===>The following messages were generated while  creating FPGA bitstream. Log file:/home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/p0/vivado/vivado.log :

                                                                          ERROR: [VPL 49-71] The board_part definition was not found for xilinx.com:zcu102:part0:3.2. The project's board_part property was not set, but the project's part property was set to xczu9eg-ffvb1156-2-e. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

                                                                          ERROR: [VPL 60-773] In '/home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/p0/vivado/vivado.log', caught Tcl error:  ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:zcu102:part0:3.2. The project's board_part property was not set, but the project's part property was set to xczu9eg-ffvb1156-2-e. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

                                                                          ERROR: [VPL 60-704] Integration error, problem rebuilding project prj

                                                                          ERROR: [VPL 60-806] Failed to finish platform linker

                                                                          ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/ahmed/Xilinx2018.2/SDx/2018.2/bin/vpl   --iprepo /home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/iprepo/repo  --iprepo /home/ahmed/Xilinx2018.2/SDx/2018.2/data/ip/xilinx  --platform /home/ahmed/Xilinx2018.2/SDx/2018.2/platforms/zcu102/zcu102.xpfm  --temp_dir /home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/p0  --output_dir /home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/p0/vpl  --input_file /home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels madd:mmult:adapter --webtalk_flag SDSoC  --remote_ip_cache /home/ahmed/Xi-W-2018.2/WK-SDX/ip_cache --xp "param:compiler.deleteDefaultReportConfigs=false" '

                                                                          sds++ log file saved as /home/ahmed/Xi-W-2018.2/WK-SDX/FirstPro/Release/_sds/reports/sds.log

                                                                          make: *** [FirstPro.elf] Error 1

                                                                          ERROR: [SdsCompiler 83-5004] Build failed

                                                                           

                                                                          ***********************************************************************************************************************************************************************************************************************************************************************

                                                                           

                                                                          get_board_parts

                                                                          alpha-data.com:adm-pcie-7v3:part0:1.0 alpha-data.com:adm-pcie-7v3:part0:1.1 alpha-data.com:adm-pcie3-ku3:part0:1.0 em.avnet.com:ultra96:part0:1.0 em.avnet.com:zed:part0:0.9 em.avnet.com:zed:part0:1.0 em.avnet.com:zed:part0:1.1 em.avnet.com:zed:part0:1.2 em.avnet.com:zed:part0:1.3 em.avnet.com:zed:part0:1.4 xilinx.com:ac701:part0:1.0 xilinx.com:ac701:part0:1.1 xilinx.com:ac701:part0:1.2 xilinx.com:ac701:part0:1.3 xilinx.com:ac701:part0:1.4 xilinx.com:kc705:part0:0.9 xilinx.com:kc705:part0:1.0 xilinx.com:kc705:part0:1.1 xilinx.com:kc705:part0:1.2 xilinx.com:kc705:part0:1.3 xilinx.com:kc705:part0:1.4 xilinx.com:kc705:part0:1.5 xilinx.com:kcu105:part0:1.0 xilinx.com:kcu105:part0:1.1 xilinx.com:kcu105:part0:1.2 xilinx.com:kcu105:part0:1.3 xilinx.com:kcu105:part0:1.4 xilinx.com:kcu116:part0:1.0 xilinx.com:kcu116:part0:1.1 xilinx.com:kcu116:part0:1.2 xilinx.com:kcu116:part0:1.3 xilinx.com:kcu1500:part0:1.0 xilinx.com:kcu1500:part0:1.1 xilinx.com:pico_m505:part0:1.0 xilinx.com:vc707:part0:1.0 xilinx.com:vc707:part0:1.1 xilinx.com:vc707:part0:1.2 xilinx.com:vc707:part0:1.3 xilinx.com:vc709:part0:1.0 xilinx.com:vc709:part0:1.1 xilinx.com:vc709:part0:1.2 xilinx.com:vc709:part0:1.3 xilinx.com:vc709:part0:1.4 xilinx.com:vc709:part0:1.5 xilinx.com:vc709:part0:1.6 xilinx.com:vc709:part0:1.7 xilinx.com:vc709:part0:1.8 xilinx.com:vcu108:part0:1.1 xilinx.com:vcu108:part0:1.2 xilinx.com:vcu108:part0:1.3 xilinx.com:vcu108:part0:1.4 xilinx.com:vcu110:part0:1.1 xilinx.com:vcu110:part0:1.2 xilinx.com:vcu110:part0:1.3 xilinx.com:vcu118:part0:2.0 xilinx.com:vcu1525:part0:1.0 xilinx.com:vcu1525:part0:1.1 xilinx.com:zc702:part0:1.0 xilinx.com:zc702:part0:1.1 xilinx.com:zc702:part0:1.2 xilinx.com:zc702:part0:1.3 xilinx.com:zc702:part0:1.4 xilinx.com:zc706:part0:1.0 xilinx.com:zc706:part0:1.1 xilinx.com:zc706:part0:1.2 xilinx.com:zc706:part0:1.3 xilinx.com:zc706:part0:1.4 xilinx.com:zcu102:part0:2.0 xilinx.com:zcu102:part0:2.1 xilinx.com:zcu102:part0:2.2 xilinx.com:zcu102:part0:3.1 xilinx.com:zcu102:part0:3.2 xilinx.com:zcu102_es2:part0:2.3 xilinx.com:zcu102_es2:part0:2.4 xilinx.com:zcu104:part0:1.0 xilinx.com:zcu104:part0:1.1 xilinx.com:zcu106:part0:2.0 xilinx.com:zcu106:part0:2.1 xilinx.com:zcu106:part0:2.2

                                                                           

                                                                          I run the command on TCL console it looks fine but I have no idea what is an issue with Xilinx SDx 2018.2

                                                                           

                                                                          Thanks

                                                                           

                                                                          Ahmed

                                                                            • Re: No Ultrazed-EG SDSoC platform supplied
                                                                              jafoste4

                                                                              Ahmed,


                                                                              When you run get_board_parts I dont see the ultrazed_eg_pciecc_production:part0:1.1 nor the xilinx.com:zcu102:part0:3.2 that your trying to target.

                                                                               

                                                                              -Josh

                                                                                • Re: No Ultrazed-EG SDSoC platform supplied
                                                                                  fasih.ahmed

                                                                                  Hi Josh

                                                                                  xilinx.com:zcu102:part0:3.2 you can see this on 2nd last line :/

                                                                                  Ahmed

                                                                                    • Re: No Ultrazed-EG SDSoC platform supplied
                                                                                      jafoste4

                                                                                      Your correct, I missed it.

                                                                                       

                                                                                      -Josh

                                                                                        • Re: No Ultrazed-EG SDSoC platform supplied
                                                                                          fasih.ahmed

                                                                                          Hi Josh,

                                                                                          I tried to run simple Matrix Multiplication example does not work I don't know why :/

                                                                                          even I re-install the 2018.2 sdx version.

                                                                                          something missing between vivado and sdx connection (IDK what) 

                                                                                          BR,

                                                                                          Ahmed

                                                                                            • Re: No Ultrazed-EG SDSoC platform supplied
                                                                                              drozwood90

                                                                                              Ahmed,

                                                                                               

                                                                                              Just going by what you have given us, the tool is saying you need to have em.avnet.com:ultrazed_eg_pciecc_production:part0:1.1 installed.

                                                                                              I posted a link where you can find that.  From your list, the tool is not seeing the BDF.  Can you look in the following folder?  Sometimes I get confused and put the files in the wrong folder.

                                                                                              Vivado/2018.2/data/boards/board_files

                                                                                              Sometimes I put them in board_parts, which is INCORRECT, especially since the error message talks about board_parts.  It needs to be board_files.

                                                                                               

                                                                                              You should see a folder in board_files called \ultrazed_3eg_pciecc with TWO folders.  a 1.0 and a 1.1.

                                                                                              These are screen captures from Windows, but they would be the SAME in Linux.

                                                                                               

                                                                                              IF that folder is there, we likely have some other issue - but I think this is just in the wrong folder, as I said, I've done this myself.  And it is a REALLY small detail to mix up.

                                                                                               

                                                                                              --Dan

                                                                                                • Re: No Ultrazed-EG SDSoC platform supplied
                                                                                                  fasih.ahmed

                                                                                                  Thanks daniel

                                                                                                  I am currently facing isssue in Sdx 2018.2 with other boards which already installed during installation

                                                                                                  but thanks for your help

                                                                                                    • Re: No Ultrazed-EG SDSoC platform supplied
                                                                                                      drozwood90

                                                                                                      Ahmed,

                                                                                                       

                                                                                                      My mistake.  When threads get this long, it is sometimes confusing to know which issue is which.

                                                                                                      So to recap, the design thinks that the tool is missing xilinx.com:zcu102:part0:3.2, but get_parts shows the xilinx.com:zcu102:part0:3.2 exists?

                                                                                                      Which Matrix multiply example are you trying?  I know as of 18.2, there are 4-5 of them now.

                                                                                                       

                                                                                                      Were you using the 102 to validate your design?  I just scrolled up and it looks like you were using the UZ-EG w/IOCC .  There was a version of the MM example for that where the BDF was called out incorrect.  If that is the case, it would be easier to just create your own design.  It really is rather quick.  You can use the TCL at the end of this to create the design.  The issue was, a long time ago, the wrong BDF was called out.  It was never caught as for the MM design the pinout doesn't matter.

                                                                                                       

                                                                                                      If you were trying to use the 102, can you test this, just start a new Vivado design, work through until you get to the part picker.

                                                                                                      Choose board, type 102 in the search bar and see what shows up.

                                                                                                       

                                                                                                      If you do not see the below, then we can understand it seems to be a tool / permissions issue.  If that shows up, something in the design could be messing up.

                                                                                                      Note the VERSION on the RIGHT hand column.  Make sure that states 3.2.

                                                                                                       

                                                                                                      I've personally seen some differences in the way the GUI and TCL works when interfacing to the tool.  It is strange, but it certainly happens.

                                                                                                       

                                                                                                      --Dan

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                      TCL DESIGN:

                                                                                                       

                                                                                                       

                                                                                                      # This script will setup and spin off the Hardware Project

                                                                                                       

                                                                                                      # From StackOverflow

                                                                                                      # https://stackoverflow.com/questions/29482303/how-to-find-the-number-of-cpus-in-tcl

                                                                                                       

                                                                                                       

                                                                                                      proc numberOfCPUs {} {

                                                                                                          # Windows puts it in an environment variable

                                                                                                          global tcl_platform env

                                                                                                          if {$tcl_platform(platform) eq "windows"} {

                                                                                                              return $env(NUMBER_OF_PROCESSORS)

                                                                                                          }

                                                                                                       

                                                                                                       

                                                                                                          # Check for sysctl (OSX, BSD)

                                                                                                          set sysctl [auto_execok "sysctl"]

                                                                                                          if {[llength $sysctl]} {

                                                                                                              if {![catch {exec {*}$sysctl -n "hw.ncpu"} cores]} {

                                                                                                                  return $cores

                                                                                                              }

                                                                                                          }

                                                                                                       

                                                                                                       

                                                                                                          # Assume Linux, which has /proc/cpuinfo, but be careful

                                                                                                          if {![catch {open "/proc/cpuinfo"} f]} {

                                                                                                              set cores [regexp -all -line {^processor\s} [read $f]]

                                                                                                              close $f

                                                                                                              if {$cores > 0} {

                                                                                                                  return $cores

                                                                                                              }

                                                                                                          }

                                                                                                       

                                                                                                       

                                                                                                          # No idea what the actual number of cores is; exhausted all our options

                                                                                                          # Fall back to returning 1; there must be at least that because we're running on it!

                                                                                                          return 1

                                                                                                      }

                                                                                                       

                                                                                                       

                                                                                                      # Change me to the location you want to put the project

                                                                                                       

                                                                                                       

                                                                                                      set _xil_proj_name_ uzegiocc_avnet

                                                                                                       

                                                                                                       

                                                                                                      cd c:/Avnet/

                                                                                                      #cd /home/training/projects/u96_SDK

                                                                                                      create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part  xczu3eg-sfva625-1-i

                                                                                                      cd ./${_xil_proj_name_}

                                                                                                       

                                                                                                       

                                                                                                      set proj_dir [pwd]

                                                                                                       

                                                                                                       

                                                                                                      # Set project properties

                                                                                                      set obj [current_project]

                                                                                                      set_property -name "board_part" -value "em.avnet.com:ultrazed_eg_iocc_production:part0:1.0" -objects $obj

                                                                                                      set_property -name "default_lib" -value "xil_defaultlib" -objects $obj

                                                                                                      set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj

                                                                                                      set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj

                                                                                                      set_property -name "dsa.board_id" -value "ultrazed_eg_iocc" -objects $obj

                                                                                                      set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj

                                                                                                      set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj

                                                                                                      set_property -name "dsa.emu_dir" -value "emu" -objects $obj

                                                                                                      set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj

                                                                                                      set_property -name "dsa.flash_offset_address" -value "0" -objects $obj

                                                                                                      set_property -name "dsa.flash_size" -value "1024" -objects $obj

                                                                                                      #set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj

                                                                                                      #set_property -name "dsa.host_interface" -value "pcie" -objects $obj

                                                                                                      #set_property -name "dsa.num_compute_units" -value "60" -objects $obj

                                                                                                      set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj

                                                                                                      #set_property -name "dsa.uses_pr" -value "1" -objects $obj

                                                                                                      set_property -name "dsa.name" -value ${_xil_proj_name_} -objects $obj

                                                                                                      set_property -name "dsa.vendor" -value "em.avnet.com" -objects $obj

                                                                                                      set_property -name "dsa.version" -value "0.0" -objects $obj

                                                                                                      set_property -name "enable_vhdl_2008" -value "1" -objects $obj

                                                                                                      set_property -name "ip_cache_permissions" -value "read write" -objects $obj

                                                                                                      set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj

                                                                                                      set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj

                                                                                                      set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj

                                                                                                      set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj

                                                                                                      set_property -name "simulator_language" -value "Mixed" -objects $obj

                                                                                                       

                                                                                                       

                                                                                                      create_bd_design "${_xil_proj_name_}"

                                                                                                      update_compile_order -fileset sources_1

                                                                                                      create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 zynq_ultra_ps_e_0

                                                                                                       

                                                                                                       

                                                                                                      create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0

                                                                                                      create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1

                                                                                                       

                                                                                                       

                                                                                                      startgroup

                                                                                                      create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0

                                                                                                      create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1

                                                                                                      endgroup

                                                                                                       

                                                                                                       

                                                                                                      apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" }  [get_bd_cells zynq_ultra_ps_e_0]

                                                                                                      startgroup

                                                                                                      set_property -dict [list CONFIG.PSU__USE__IRQ0 {1}] [get_bd_cells zynq_ultra_ps_e_0]

                                                                                                      set_property -dict [list CONFIG.PSU__USE__IRQ1 {1}] [get_bd_cells zynq_ultra_ps_e_0]

                                                                                                      set_property -dict [list CONFIG.PSU__FPGA_PL1_ENABLE {1} CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250}] [get_bd_cells zynq_ultra_ps_e_0]

                                                                                                      #as with MiniZed, need to disable UART0 in order to bring STDIO to correct port

                                                                                                      #set_property -dict [list CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0}] [get_bd_cells zynq_ultra_ps_e_0]

                                                                                                      set_property -dict [list CONFIG.PSU__USE__M_AXI_GP0 {1} CONFIG.PSU__USE__M_AXI_GP1 {1}] [get_bd_cells zynq_ultra_ps_e_0]

                                                                                                      endgroup

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                      set_property -dict [list CONFIG.NUM_PORTS {1}] [get_bd_cells xlconcat_0]

                                                                                                      set_property -dict [list CONFIG.NUM_PORTS {1}] [get_bd_cells xlconcat_1]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins proc_sys_reset_1/ext_reset_in]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins proc_sys_reset_0/ext_reset_in]

                                                                                                      connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk1] [get_bd_pins proc_sys_reset_1/slowest_sync_clk]

                                                                                                      connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0]

                                                                                                      connect_bd_net [get_bd_pins xlconcat_1/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq1]

                                                                                                      validate_bd_design

                                                                                                      regenerate_bd_layout

                                                                                                      make_wrapper -files [get_files ./${_xil_proj_name_}.srcs/sources_1/bd/${_xil_proj_name_}/${_xil_proj_name_}.bd] -top

                                                                                                      add_files -norecurse ./${_xil_proj_name_}.srcs/sources_1/bd/${_xil_proj_name_}/hdl/${_xil_proj_name_}_wrapper.v

                                                                                                       

                                                                                                       

                                                                                                      # Everything above here is just plain Vivado project

                                                                                                      # All SDSoC below here

                                                                                                       

                                                                                                       

                                                                                                      set_property PFM_NAME "em.avnet.com:av:${_xil_proj_name_}:1.0" [get_files ./${_xil_proj_name_}.srcs/sources_1/bd/${_xil_proj_name_}/${_xil_proj_name_}.bd]

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                      set_property PFM.CLOCK {\

                                                                                                      pl_clk0 {id "0" is_default "true" proc_sys_reset \

                                                                                                      "proc_sys_reset_0"}\

                                                                                                      pl_clk1 {id "1" is_default "false" proc_sys_reset \

                                                                                                      "proc_sys_reset_1"}\

                                                                                                      } [get_bd_cells /zynq_ultra_ps_e_0]

                                                                                                       

                                                                                                       

                                                                                                      #set_property PFM.AXI_PORT { \

                                                                                                      #M_AXI_GP0 {memport "M_AXI_GP"} \

                                                                                                      #M_AXI_GP1 {memport "M_AXI_GP"} \

                                                                                                      #S_AXI_ACP {memport "S_AXI_ACP"} \

                                                                                                      #S_AXI_HP0 {memport "S_AXI_HP"} \

                                                                                                      #S_AXI_HP1 {memport "S_AXI_HP"} \

                                                                                                      #S_AXI_HP2 {memport "S_AXI_HP"} \

                                                                                                      #S_AXI_HP3 {memport "S_AXI_HP"} \

                                                                                                      #} [get_bd_cells /zynq_ultra_ps_e_0]

                                                                                                       

                                                                                                       

                                                                                                      #set_property PFM.AXI_PORT { \

                                                                                                      #                                M_AXI_HPM0_LPD {memport "M_AXI_GP"} \

                                                                                                      #                                M_AXI_HPM1_FPD {memport "M_AXI_GP"} \

                                                                                                      #                                S_AXI_HP0_FPD {memport "S_AXI_HP"} \

                                                                                                      #                                S_AXI_HP1_FPD {memport "S_AXI_HP"} \

                                                                                                      #                                S_AXI_HP2_FPD {memport "S_AXI_HP"} \

                                                                                                      #                                S_AXI_HP3_FPD {memport "S_AXI_HP"} \

                                                                                                      #                            } [get_bd_cells /zynq_ultra_ps_e_0]

                                                                                                       

                                                                                                       

                                                                                                        set_property PFM.AXI_PORT { \

                                                                                                        M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory ""} \

                                                                                                        M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory ""} \

                                                                                                        M_AXI_HPM0_LPD {memport "M_AXI_GP" sptag "" memory ""} \

                                                                                                        S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory ""} \

                                                                                                        S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory ""} \

                                                                                                        S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory ""} \

                                                                                                        S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory ""} \

                                                                                                        S_AXI_LPD {memport "MIG" sptag "" memory ""}\

                                                                                                        } [get_bd_cells /zynq_ultra_ps_e_0]

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                       

                                                                                                      set intVar []

                                                                                                      for {set i 0} {$i < 8} {incr i} {

                                                                                                      lappend intVar In$i {}

                                                                                                      }

                                                                                                      set_property PFM.IRQ $intVar [get_bd_cells /xlconcat_0]

                                                                                                      set_property PFM.IRQ $intVar [get_bd_cells /xlconcat_1]

                                                                                                      #  set_property PFM.IRQ { \

                                                                                                      #  In0 {} In1 {} In2 {} In3 {} In4 {} In5 {} In6 {} In7 {} \

                                                                                                      #  } [get_bd_cells /xlconcat_0]

                                                                                                       

                                                                                                       

                                                                                                      save_bd_design

                                                                                                      launch_runs impl_1 -to_step write_bitstream -jobs [numberOfCPUs]

                                                                                                      wait_on_run impl_1

                                                                                                      write_dsa ${_xil_proj_name_}.dsa -include_bit

                                                                                                      validate_dsa ${_xil_proj_name_}.dsa -verbose

                                                                                                       

                                                                                                       

                                                                                                      file mkdir ./${_xil_proj_name_}.sdk

                                                                                                      file copy -force ./${_xil_proj_name_}.runs/impl_1/${_xil_proj_name_}_wrapper.sysdef ./${_xil_proj_name_}.sdk/${_xil_proj_name_}_wrapper.hdf