2 Replies Latest reply on Mar 15, 2019 12:32 AM by macha10

    EMBV PYTHON 1300C FRAME BUFFER reference design

    macha10

      Hello,

       

      I would like to reexecute the reference design given with the EMBV_python_1300C kit (http://zedboard.org/support/design/6251/51). I followed all steps listed in the EMBV_PYTHON_1300C_FRAME_BUFFER_tutorial_2015_4-01.pdf", but when implementing I got a lot of warnings, telling that there is no FIFO_GENERATOR 13.0 in the Onsemi_vita_cam and Onsemi_vita_SPI IP cores. After googling, I found that an update of this project under Vivado 2017.2 uses an XPM_FIFO, which needs many asynchronous clocks. I used this update and the implementation process stops, when executing these next lines of the .XDC constraint file:

      create_clock -period 3.703 -name vita_ser_clk [get_ports IO_PYTHON_CAM_clk_out_p]

      # Define asynchronous clock domains

      set_clock_groups -asynchronous -group [get_clocks clk_fpga_0]\

        -group [get_clocks clk_fpga_1]\ 

        -group [get_clocks clk_out1_embv_p1300c_clk_wiz_0_0]\

        -group [get_clocks vita_clk]\

        -group [get_clocks CLKDIV_c_0]

      I' m getting these critical warnings during the design creation and implementation

      connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins avnet_hdmi_out_0/clk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins onsemi_vita_cam_0/clk] [get_bd_pins rst_PS7_0_108M/slowest_sync_clk] [get_bd_pins v_axi4s_vid_out_0/vid_io_out_clk] [get_bd_pins v_tc_0/clk] [get_bd_pins v_vid_in_axi4s_0/vid_io_in_clk]

      WARNING: [BD 41-1731] Type mismatch between connected pins: /avnet_hdmi_out_0/clk(undef) and /clk_wiz_0/clk_out1(clk)

      WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /onsemi_vita_cam_0/clk(undef)

       

       

      connect_bd_net -net PS7_0_FCLK_CLK2 [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins onsemi_vita_cam_0/clk200] [get_bd_pins PS7_0/FCLK_CLK2]

      WARNING: [BD 41-1731] Type mismatch between connected pins: /onsemi_vita_cam_0/clk200(undef) and /PS7_0/FCLK_CLK2(clk)

       

      connect_bd_net -net rst_PS7_0_76M_peripheral_reset [get_bd_pins avnet_hdmi_out_0/reset] [get_bd_pins rst_PS7_0_76M/peripheral_reset] [get_bd_pins v_axi4s_vid_out_0/vid_io_out_reset] [get_bd_pins v_vid_in_axi4s_0/vid_io_in_reset]

      WARNING: [BD 41-1731] Type mismatch between connected pins: /avnet_hdmi_out_0/reset(undef) and /rst_PS7_0_76M/peripheral_reset(rst)

       

       

      4) After executing the microzed_preset.tcl script, I got these warnings, so why these values are negatives, they cause a failure in timing constraint after place an route process

      CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.

      CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.072 . PS DDR interfaces might fail when entering negative DQS skew values.

      CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.

      CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.072 . PS DDR interfaces might fail when entering negative DQS skew values.

      CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.

      CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.072 . PS DDR interfaces might fail when entering negative DQS skew values.

       

      After Synthesis (out of context module runs)

      Warning:

      [Vivado 12-507] No nets matched 'FCLK_CLK0'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":120]

      [Vivado 12-507] No nets matched 'FCLK_CLK1'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":121]

      [Vivado 12-507] No nets matched 'FCLK_CLK2'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":122]

       

      [Vivado 12-627] No clocks matched 'clk_fpga_0'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-627] No clocks matched 'clk_fpga_1'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-627] No clocks matched 'clk_out1_embv_p1300c_clk_wiz_0_0'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-627] No clocks matched 'vita_clk'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-627] No clocks matched 'CLKDIV_c_0'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

       

      CRITICAL WARNING:

      [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clk_fpga_1]'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clk_out1_embv_p1300c_clk_wiz_0_0]'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks vita_clk]'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

      [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks CLKDIV_c_0]'. ["/home/nmazc/vivado_projects/video_acquisition/embv_python1300.xdc":129]

       

      generating bitstream

      [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

      So could you, please, help me?