0 Replies Latest reply on Mar 27, 2019 1:52 PM by avib71



      I've built an IP in the system generator, My logic work with 40MHz system clock, I have Gateway input/output which config as AXI4-Light register.

      in other words the Implementation Interface on the Xilinx gateway blocks to "AXI4-Lite" which gives me the interface.I like to separate the AXI4-light clock to work faster (100-200MHz)

      and to keep my system clock 40MHz.

      Is there anyway I can separate the clocks in system generator so that I can run the AXI4-Lite interface at 100MHz, while I run the waveform generation at 40MHz?