0 Replies Latest reply on Apr 15, 2019 2:53 AM by bkamen

    Microzed-020 w/ON-Semi VITA/Python 1300

    bkamen

      Hey Avnet Devs,

      I have a whole Verilog core I've written (moving images to Linux via DMA) for a rather custom science application that's been working fine with the VITA monochrome parallel imager.

      I've finished adding support for the VITA1300 (mono) LVDS version (because I had one already populated) and that's working as well. (so that should rule out bit/word alignment issues)

      From there, I added support for the Python1300 (using all 4 lanes) -- and seem to have things mostly working except for sync issues.

      Both imagers are being used in 8bit mode. So the VITA is running at 62/248MHz and the Python is running at 72/288MHz.

      My SYNC channel seems to be fine. And D0-D3, only one channel seems to phase in and out of sync.

      So my question is:

      All the VCCO are 3.3V. I read on the XIlinx forums that setting for LVDS_25 is ok as long as the bank is not doing any output, but RTERM ends up being the equivalent of about 80ohms.
      I went looking at the Avnet python1300 camera board pdf (BD-CAM-PYTHON1300C-B User Guide - v1.0-1.pdf) which has pass-thru LVDS connections with a recommendation to use LVDS_25 on the Xilinx.
      But there's no mention if the camera board is doing any translation to 2.5V from the python's 3.3VDDio requirement.

      So I'm currently trying to rule out that I'm running into a poor termination issue. We've been pretty careful about PCB layout with the only goof being that some data lines ended up in a different bank from the other.
      (Some are on Bank34 and some on Bank35.) -- but the VITA works fine... so while I'm not ruling that issue out either, at 62/248MHz, the VITA works fine.

      I'm not sure if the increase in LVDS clock is starting to bump into hardware issues.... so I looked at the PDF above but it doesn't really answer my question.

      This is my first LVDS design... so I'm not sure how sensitive things can be between voltage, termination, speed and Xilinx.

      Thanks,

      -Ben

      p.s. I have some other questions about common practices for monitoring and handling re-sync when sync/crc errors are detected.
      FWIW, I'm using the bit-deskew engine from Xapp1017.