0 Replies Latest reply on May 13, 2019 7:13 AM by youngk

    UltraZed-EG SOM and IO carrier clock configuration

    youngk

      Hi,

      I am testing UltraZed-EG SOM and IO carrier. But I couldn't get PL-SYSCLK (300MHz) working. I put jumper setting to default mode as following;

       

      J1 and J2 placed on pins 1-2 and JP1 is not installed.

       

      I put down simple VHDL test code and xdc file below. Please review and help me out.

      Thanks,

      Young

      -------------------------------------------------------------------------------------------------------------------------------------------------------

      entity test is

      port (

                sysclk_p : in std_logic;

                sysclk_n : in std_logic;

                tp_1 : out std_logic;    --

      --leds

               pl_led1 : out std_logic;    --

               pl_led2 : out std_logic    --

              );

      end test;

      architecture structure of test is

       

      ------*** signal declaration ***

      signal sysclk : std_logic := '0';-- 

      signal cnt: std_logic_vector(15 downto 0) := (others => '0');--

       

      --#######################################################################################

      begin

      --=====================================================================

      --Test signals

      --=====================================================================

      pl_led1 <= cnt(15);

      pl_led2 <= '1';

      tp_1 <= cnt(10);

      --=====================================================================

      --components instantiation

      --=====================================================================

      IBUFDS_1 : IBUFDS

      generic map (

      DQS_BIAS => "FALSE" -- (FALSE, TRUE)

      )

      port map (

      O => sysclk, -- 1-bit output: Buffer output

      I => sysclk_p, -- 1-bit input: Diff_p buffer input (connect directly to top-level port)

      IB => sysclk_n -- 1-bit input: Diff_n buffer input (connect directly to top-level port)

      );

       

      process (sysclk)

      begin

           if rising_edge(sysclk) then

                cnt <= cnt + 1;

           end if;

      end process;

      end structure;

      --------------------------------------------------------------------------------------------------------------------------------------------------

      test.xdc

      ----------------------------------------------------------------------------------------------------------------------------------------------------

      set_property IOSTANDARD LVCMOS18 [get_ports pl_led1]

      set_property IOSTANDARD LVCMOS18 [get_ports pl_led2]

       

       

      set_property IOSTANDARD LVDS [get_ports sysclk_p]

      set_property IOSTANDARD LVDS [get_ports sysclk_n]

       

       

      set_property IOSTANDARD LVCMOS18 [get_ports tp_1]

       

       

      #

      set_property PACKAGE_PIN R7 [get_ports pl_led1]

      set_property PACKAGE_PIN T5 [get_ports pl_led2]

       

       

       

       

      set_property PACKAGE_PIN N4 [get_ports sysclk_p]

      set_property PACKAGE_PIN N3 [get_ports sysclk_n]

       

       

      set_property PACKAGE_PIN E2 [get_ports tp_1]

      • Reply