I found thisEncode needed Voltage for an AD9057 , which shows this forum has folks who know about ADC and AD9057, so I ask my questions here:
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9057.pdf has an Evaluation Board circuit in it.
I've built a circuit (Video Capture Card on this VGA Videowall page), somewhat like the Evaluation Board.
This produces digitised data, which then goes into a Video Framestore Card, which can rearrange the picture and then outputs it to VGA.
On the Video Capture Card, an input signal (VGA 640x480, 0 to 0.7V) is put through 3 AD8041s to map it to 3.0 to 2.0V, which then enters 3 corresponding AD9057s.
The AD9057 ENCODE signal comes from the Video Framestore Card.
The circuit board separates the analog and digital parts, with separate power for the analog and digital sides.
It is a 2 layer board but the analog part uses power and ground fills in the gaps around the components to try to compensate for not having a full 4 layer board with full ground and power planes.
I set up a Raspberry Pi to output a 640x480 VGA 256 shades-of-grey testcard.
I am only using the top 3 bits of the 8 bits captured of R,G and B, so I expect to get 8 shades with a little noise on the transitions - but actually I see a lot of noise
I did expect noise, but as I am only taking the top 3 bits, I was hoping most of the noise would be the in 5 bits I'm ignoring.
The Video Framestore Card is purely digital and uses a Cmod A7 (Development board for Cmod A7 Xilinx Artix-7 FPGA).
It generates the ENCODE signal which is sent to the Video Capture Card.
The digital video from Video Capture Card is converted from 5V to 3.3V using 4050 level-shifters and passed into the Cmod.
The Cmod rearranges the video, and then uses a resistor ladder DACs to convert it back to VGA.
This card works perfectly - I've testing using internally generated testcard data, without connecting the capture circuit.
7V enters the boards, and I use regulators to make 5V and then 3.3V, which I think is reasonably smooth.
Since designing the circuit, I've since read https://pyfn.com/PDF/electronics_pdfs/noise/controlling_noise.pdf which says I should use a ground plane, but not power planes, instead use power traces.
Given my design only uses a power plane for the analog part, and keeps the digital power and signals away from that, I don't know how much things would get better if I changed it.
The AD9057 Evaluation Board take the encode signal and puts it through 4 NANDs, and feeds these to the AD9057 ENCODE, a 74ACQ574 latch clock, and other places.
Whats the rationale for a) having the NANDs, and b) using a different NAND for driving each downstream thing.
Could it be that the output of a NAND is somehow less noisy?
I've read somewhere that some ADCs are sensitive to noise in their digital inputs, could that be it?
Wouldn't using different NANDs in this "star" arrangement, introduce the possibility of skew in the outputs, or is this less of a concern considering signal trace lengths would vary anyway?
The AD9057 Evaluation Board clocks a 74ACQ574 latch at the same time as triggering the ENCODE - how significant is this?
I realise that if the FPGA sampled the output of the AD9057 as it was changing, that would be a bad thing.
However, in my current design, when the FPGA samples, it will be sampling data output by the AD9057 a few ns before (courtesy of propagation delay of level shifter), and this should be squarely in the middle of a period of time in which the AD9057 outputs are stable.
I have tried changing exactly when the FPGA samples, which didn't seem change the amount of noise.
At the moment, the ADCs use 5V on the digital side, meaning that I must level shift them before feeding them to the CMod and thus the Artix FPGA.
This introduces a delay and a component I don't really need - I can use 3.3V on the digital side.
I don't know if this will make things any better.
At the moment I have 2 boards, with a short ribbon connector between them.
The ENCODE signal, and the digitised data signals flow over this cable.
I'm wondering if I can fit everything on one board, and avoid this cable, which would be one less thing radiating 25MHz digital signals.
At the moment, I am thinking I should just use a ground fill (reluctant to spend serious $ on 4-layers), I should put encode through a buffer gate (eg: NAND), I should latch the ADC digital outputs, I should switch to using 3.3V on the digital side of the ADC and remove the level shifter, I should redesign to put everything on one board.
What do you think? Thanks in advance for any feedback.
P.S. This is a hobby, and I have zero formal training in any of this :-)