14 Replies Latest reply on Sep 7, 2019 8:04 PM by clem57

    AD9057, a circuit like the Evaluation Board, sources of noise

    andykey

      I found thisEncode needed Voltage  for an AD9057 , which shows this forum has folks who know about ADC and AD9057, so I ask my questions here:

       

      https://www.analog.com/media/en/technical-documentation/data-sheets/AD9057.pdf has an Evaluation Board circuit in it.

       

      I've built a circuit (Video Capture Card on this VGA Videowall page), somewhat like the Evaluation Board.

      This produces digitised data, which then goes into a Video Framestore Card, which can rearrange the picture and then outputs it to VGA.

       

      On the Video Capture Card, an input signal (VGA 640x480, 0 to 0.7V) is put through 3 AD8041s to map it to 3.0 to 2.0V, which then enters 3 corresponding AD9057s.

      The AD9057 ENCODE signal comes from the Video Framestore Card.

      The circuit board separates the analog and digital parts, with separate power for the analog and digital sides.

      It is a 2 layer board but the analog part uses power and ground fills in the gaps around the components to try to compensate for not having a full 4 layer board with full ground and power planes.

      I set up a Raspberry Pi to output a 640x480 VGA 256 shades-of-grey testcard.

      I am only using the top 3 bits of the 8 bits captured of R,G and B, so I expect to get 8 shades with a little noise on the transitions - but actually I see a lot of noise

      I did expect noise, but as I am only taking the top 3 bits, I was hoping most of the noise would be the in 5 bits I'm ignoring.

       

      The Video Framestore Card is purely digital and uses a Cmod A7 (Development board for Cmod A7 Xilinx Artix-7 FPGA).

      It generates the ENCODE signal which is sent to the Video Capture Card.

      The digital video from Video Capture Card is converted from 5V to 3.3V using 4050 level-shifters and passed into the Cmod.

      The Cmod rearranges the video, and then uses a resistor ladder DACs to convert it back to VGA.

      This card works perfectly - I've testing using internally generated testcard data, without connecting the capture circuit.

       

      7V enters the boards, and I use regulators to make 5V and then 3.3V, which I think is reasonably smooth.

       

      Thoughts:

       

      1.

      Since designing the circuit, I've since read https://pyfn.com/PDF/electronics_pdfs/noise/controlling_noise.pdf  which says I should use a ground plane, but not power planes, instead use power traces.

      Given my design only uses a power plane for the analog part, and keeps the digital power and signals away from that, I don't know how much things would get better if I changed it.

       

      2.

      The AD9057 Evaluation Board take the encode signal and puts it through 4 NANDs, and feeds these to the AD9057 ENCODE, a 74ACQ574 latch clock, and other places.

      Whats the rationale for a) having the NANDs, and b) using a different NAND for driving each downstream thing.

      Could it be that the output of a NAND is somehow less noisy?

      I've read somewhere that some ADCs are sensitive to noise in their digital inputs, could that be it?

      Wouldn't using different NANDs in this "star" arrangement, introduce the possibility of skew in the outputs, or is this less of a concern considering signal trace lengths would vary anyway?

       

      3.

      The AD9057 Evaluation Board clocks a 74ACQ574 latch at the same time as triggering the ENCODE - how significant is this?

      I realise that if the FPGA sampled the output of the AD9057 as it was changing, that would be a bad thing.

      However, in my current design, when the FPGA samples, it will be sampling data output by the AD9057 a few ns before (courtesy of propagation delay of level shifter), and this should be squarely in the middle of a period of time in which the AD9057 outputs are stable.

      I have tried changing exactly when the FPGA samples, which didn't seem change the amount of noise.

       

      4.

      At the moment, the ADCs use 5V on the digital side, meaning that I must level shift them before feeding them to the CMod and thus the Artix FPGA.

      This introduces a delay and a component I don't really need - I can use 3.3V on the digital side.

      I don't know if this will make things any better.

       

      5.

      At the moment I have 2 boards, with a short ribbon connector between them.

      The ENCODE signal, and the digitised data signals flow over this cable.

      I'm wondering if I can fit everything on one board, and avoid this cable, which would be one less thing radiating 25MHz digital signals.

       

      At the moment, I am thinking I should just use a ground fill (reluctant to spend serious $ on 4-layers), I should put encode through a buffer gate (eg: NAND), I should latch the ADC digital outputs, I should switch to using 3.3V on the digital side of the ADC and remove the level shifter, I should redesign to put everything on one board.

       

      What do you think? Thanks in advance for any feedback.

       

      {{{ Andy

       

       

      P.S. This is a hobby, and I have zero formal training in any of this  :-)

        • Re: AD9057, a circuit like the Evaluation Board, sources of noise
          shabaz

          Hi Andy,

           

          There was  a lot of information and I only quickly scanned (so apologies if I've missed something you may have already mentioned) but if you're seeing noise on the top three bits, then there's a good chance that noise isn't really there, and that you're reading in data on a wrong clock edge, or not observing setup/hold times somewhere, resulting in some bits being read in transition. You mention concern over delays due to logic translation etc., but the design should be clocked, so that you're reading data at more defined times.

          It could be something else, but you may need an oscilloscope to confirm stuff like supply rails and signal quality. You could even try a low-cost logic analyzer if there is no 'scope available, but be prepared to be suspicious of the logic analyzer output, if you're unsure of the signal quality or absence of clock to read in the data into the analyzer at defined times. Also, you mention there are op amps before the ADC, so that is good, but worth checking the signal quality there too, just to confirm that the signal isn't getting loaded or noise or other anomaly there.

          Also, even connectors/cable cannot always be trusted, e.g. bad IDC cable. I recently had a frustrating issue trying to problem-solve a data bus using 0.1" headers that I couldn't get to the bottom of until I made a new cable.. I believe the connector socket was perhaps oxidised or something, despite it being a decent brand connector, it was >10 years old. I threw out all of them after seeing that!

          2 of 2 people found this helpful
          • Re: AD9057, a circuit like the Evaluation Board, sources of noise
            jc2048

            Why did you choose very old, single, flash converter parts for your design?

             

            Something like this with three ADCs, sync processing, and line-locked clock all in the one package would suit you much better

             

            https://www.analog.com/media/en/technical-documentation/data-sheets/AD9984A.pdf

            2 of 2 people found this helpful
            • Re: AD9057, a circuit like the Evaluation Board, sources of noise
              jc2048

              Now I've got a bit more time, here are some thoughts about your actual questions.

               

              When the input signal is close to the transition between two of your eight levels, then even a small amount of noise on the signal throws it back and forward between the two levels. That's very much more noticeable than if you had 256 levels and the noise is moving you between two or three levels that are barely perceptably different.

               

              I'd think about feeding all the data into your FPGA and processing it there to give the final 3 bits.

               

              To see how good (or bad) the analogue side is you need to put a oscilloscope on it rather than guessing from what you see at the end on the screen.

               

              1.
              Since designing the circuit, I've since read https://pyfn.com/PDF/electronics_pdfs/noise/controlling_noise.pdf  which says I should use a ground plane, but not power planes, instead use power traces.
              Given my design only uses a power plane for the analog part, and keeps the digital power and signals away from that, I don't know how much things would get better if I changed it.

              Bit difficult to comment without seeing your circuit or your layout.

               

              2.
              The AD9057 Evaluation Board take the encode signal and puts it through 4 NANDs, and feeds these to the AD9057 ENCODE, a 74ACQ574 latch clock, and other places.
              Whats the rationale for a) having the NANDs, and b) using a different NAND for driving each downstream thing.
              Could it be that the output of a NAND is somehow less noisy?
              I've read somewhere that some ADCs are sensitive to noise in their digital inputs, could that be it?
              Wouldn't using different NANDs in this "star" arrangement, introduce the possibility of skew in the outputs, or is this less of a concern considering signal trace lengths would vary anyway?

              The fact that the gates are NANDs isn't really a factor. Whoever designed it just chose them because they needed four gates in one package and at that time the most commonly used device with four gates in one package was the quad NAND one. An obvious reason for one package is that the gates then all have fairly similar characteristics (particularly the propagation delay) and tend to track each other with supply voltage and temperature variation.

               

              Evaluation boards aren't suggested or recommended circuits, they existed to characterise the device. The semiconductor manufacturers were narrowly focused on that and sometimes they don't even represent good design, let alone how you'd design for commercial manufacture where you also have to design to meet regulatory standards (such as safety, susceptibility and emissions, etc) as well as reliable circuit operation. In this case, the intention is to buffer the clock whilst ensuring that the clock edges to the four parts the clock is driving line up, with a 'good enough' shape to the edge to cleanly clock the parts. It worked on the board but something that may not be obvious is that it worked because the gates are very close to the parts being driven. If you extended the length of the clock traces, the edges would start to get quite ragged. In a real design you'd want to terminate the clock traces reasonably accurately. In this case, where you have the clock distribution done as a star, the most natural way to do that is with series termination.

               

              3.
              The AD9057 Evaluation Board clocks a 74ACQ574 latch at the same time as triggering the ENCODE - how significant is this?
              I realise that if the FPGA sampled the output of the AD9057 as it was changing, that would be a bad thing.
              However, in my current design, when the FPGA samples, it will be sampling data output by the AD9057 a few ns before (courtesy of propagation delay of level shifter), and this should be squarely in the middle of a period of time in which the AD9057 outputs are stable.
              I have tried changing exactly when the FPGA samples, which didn't seem change the amount of noise.

              My reading of the datasheet is that it doesn't have an internal latch. So you need to take the output of the ADC at the time they specify (at the next clock edge), which means either putting in a part like the one on the evaluation board or using your FPGA to do the same job.

               

              4.

              At the moment, the ADCs use 5V on the digital side, meaning that I must level shift them before feeding them to the CMod and thus the Artix FPGA.
              This introduces a delay and a component I don't really need - I can use 3.3V on the digital side.
              I don't know if this will make things any better.

              I'd say using the slow 4050 part for translation is a real liability. Look at the propagation delay time for the part - it's almost the clock period. It's possible that what you've got works by accident (because it's more or less a clock period), but then that's at room temperature, with a particular part, etc, and it will probably come back to haunt you. If the ADC can work at 3.3V on the digital side, then why not do that.

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                • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                  andykey

                  First, thanks to everyone who has replied.

                   

                  shabaz, ok, so removing the ADC->FPGA evel shifting removes a source of delay, but by that argument, adding a 74ACQ574 latch would seem to add some back in again, so I should latch using the FPGA.

                  I have a very primitive oscilliscope and logic analyser, which I don't think reach the 25MHz rate I'd need to get a proper look, but I take the point.

                  Redesigning to put everything on one board will remove the connector issues.

                   

                  jc2048, the AD9984A part is considerably beyond the level of sophstication I need (and currently understand).

                  Cost and use of the latest technology standards is not really a factor for this project.

                  Lots of good comments, and agreement with shabaz.

                  The link shared above does include pictures of the PCBs (so you can see the ground/power fills, and the fact analog and digital are separated), and immediately prior are links to .svg plots of the KiCad schema, and in fact the whole project is downloadable.

                  But I guess the thing here is that I simply kept analog and digital apart, let Freeroute do its thing, and added fills - I didn't hand route.

                   

                  Thanks again for the feedback, I think I know enough for my next iteration...

                   

                  {{{ Andy

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                    • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                      shabaz

                      Hi Andy,

                       

                      Is the circuit and PCB design you're using as here? VGA Videowall

                      If so, it is surprising they are using an ancient IC for level shifting. jc2048 is right, the delay through that chip is very high. It's perhaps around 50nsec (the datasheet doesn't specify for 3.3V).

                      Something like SN74LVC244A is better, intended for 3.3V, and ~10 times faster.

                      I've prototyped logic to run at ~25MHz just with jumper wires, so although a good PCB design helps, autorouting is possibly acceptable for an initial prototype too. However, decoupling is still important.

                      There's a comment about capacitors highlighted in red in the screenshot below, I don't know which it refers to, but by ADC1/2/3 they are super-important, and each op-amp will require it too, but I can't see space for capacitors for the opamps from this screenshot (maybe they are on the underside).

                      Also, just 100nF is likely insufficient, and (say) 10uF polarized cap should be added too, close to each ADC/Opamp pair. This won't be perfect, but at least will test if decoupling is an issue, until the next board design.

                       

                      EDIT: Found the schematic (pasted below to make it easier to refer to). There's no decoupling near the op amps, they could be severely misbehaving. A 100nF capacitor should be soldered on the PCB (e.g. on the underside) directly across the supply pins. Also, some higher capacitance as mentioned should also be placed nearby (it seems the closest capacitance is the 4700uF at the voltage regulator, but that didn't need to be so high, 470uF would have been fine, and instead some 10uF or 100uF capacitors closer to the op amp and ADC would be needed.

                      EDIT 2: Also, the gain adjustment is unconventional, and should be changed on a later iteration. As it stands, wiper noise during adjustment is going to cause issues, maybe instability while adjusting too. The trimmer could be removed from where it is, and instead placed where R9 or R11 is with the wiper connected to one end of the potentiometer, and possibly another resistor or two to set the limits. Anyway, that is for a second board update, perhaps not important to your immediate issue.

                      1 of 1 people found this helpful
                        • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                          andykey

                          Yes, you found the circuit. I think I'm going to need to learn how to copy pictures into this forum, to make things easier for everyone.

                           

                          I think I have misread the 74HC4050 datasheet, I didn't realise it was that bad.

                          But this will be removed from my next iteration, so that problem will go away.

                           

                          There has always been decoupling capacitors on the ADCs.

                          The "extra" capacitors are C15 (4700uF), C14 (0.01uF) and C10 (4700uF), relating to power regulation, and make no difference if populated.

                          I have seen various reference power regulation circuits, and wondered if I needed more capacitance in them in case the output voltage (which the ADC reference voltage is derived from) wasn't as smooth as it should be. I didn't want 50 Hz UK mains power v 60 Hz VGA beats being visible as ripples on the screen.

                          But your big spot here is that I had missed the need for decoupling around the op-amps - I'll fix that.

                          In fact I can solder 100nF across the opamp, and see what that does very easily, and will do that after posting this message.

                           

                          The gain adjustment, eg: R9 (5.6K), RV2 (2.2K), R11 (8.2K) is deliberate.

                          I wanted the full sweep of the trimmer to fine tune the ratio 5.6+x:8.2+2.2-x, ie: 5.6:10.4 to 7.8:8.2.

                          I didn't want turning the trimmer all the way to one side or other to cause either side to become close to 0.

                          I know what the ratio should be under perfect conditions, I'm just conscious resistor tolerances etc aren't quite perfect, so wanted some fine tuning.

                          I accept that moving the wiper can cause noise, but I wasn't expecting noise once I put in the "right" position, and left it there?

                           

                          {{{ Andy

                          2 of 2 people found this helpful
                            • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                              shabaz

                              Hi Andy,

                               

                              All of the capacitors around the LM7805 are not needed, just a single smaller input capacitor, perhaps 100uF is fine, and a single output capacitor, maybe 10uF, both normal polarized caps. But there should be some more capacitance near the op amps, the datasheet specifies 10uF as well as 100nF.

                              Regarding the trimmer, it's possible to come up with an arrangement using fixed resistors, and a variable resistor, to get the gain you need (i.e. use resistors in parallel or series), without needing to have the potentiometer as currently located. It's up to you, generally I'm wary of trying unusual design patterns when a usual one works - in this case personally I would not do it because of reliability. If the trimmer fails with the wiper open circuit, then the output is unpredictable. With an alternate topology (wiper connected to one end of the trimmer) then that failure still keeps the circuit functioning, with the resistance becoming equal to the maximum trimmer value. Anyway, it is minor for a consumer/hobby design, and maybe it's an anachronistic suggestion too, since trimmers are a lot more reliable today than the ancient open-frame designs that used to exist.

                              Incidentally since there is a desired precise ratio, maybe no trimming is needed (I'm not knowledgeable on VGA so I'm guessing, so please ignore this if you've already investigated). 1% resistors are low-cost, and several can be paralleled to reach the values you need if it is some non-standard resistance, and this could be cheaper than trimmers, and eliminates three adjustments. It is hard to fine-tune a single-turn potentiometer sometimes (depending on the range) so perhaps 1% tolerance on the resistors might end up being more precise anyway (again just a guess). If you want to use parallel resistors, there is an online calculator.

                               

                              Also (looking more around the circuit now : ) if you experience weird faint patterns/movement on the image at any point, it could be worth adding a ferrite core to the PSU supply line, and also replacing R16 from a zero-ohm resistor, to a ferrite beadferrite bead (will need a bit more space on the PCB). Also the 7805 will likely need a small heatsink, maybe you've already planned for it.

                              2 of 2 people found this helpful
                          • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                            jc2048

                            But I guess the thing here is that I simply kept analog and digital apart, let Freeroute do its thing, and added fills - I didn't hand route.

                            Just my own preference, but I wouldn't ever autoroute a mixed-signal layout like this. The video amplifier you are using has a small-signal bandwidth of 160MHz so it's wise to follow the layout guidance in the datasheet - things like keeping the input traces very short and cutting the planes away from the input pins. Your autorouter, however clever it might be, probably doesn't understand the effect of circuit parasitics, nor how to place and route decoupling and stuff like that.

                             

                            Did you consider making the analogue side surface mount? The SMD package behaves better than the DIP one (other than power dissipation, which you'd have to look at), and it means the whole thing could be more compact. You'd also find getting precision parts for the resistors easier (1% cost next to nothing and 0.1% parts aren't too expensive any more either).

                             

                            I'd have considered a separate regulator for the analogue 5V.

                             

                            Is the power shared with the FPGA end? If not, you need to consider what happens if one supply is there and the other isn't (you can sometimes end up with one end being powered through the I/O pin protection diodes of the other).

                             

                            If there's not much setup time on the data, you might also want to look at series termination on the lines going off to the FPGA. For a commercial design you'd do it anyway for signal integrity reasons and as part of trying to quieten it down for EMC reasons [except, of course, you wouldn't have the ribbon cable - you'd make it all one board]. Do you have grounds interleaved with the data on the ribbon cable?

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                        • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                          andykey

                          I refactored both analog and digital boards into a single board, which does away with the ribbon cable.

                          I ensured the output of the ADCs was 3.3V so it could be sent directly into the Cmod A7 (with Artix 7) model, without going via slow 74HC4050 level shifters.

                          I made a mistake, so still have to pass hsync and vsync signals through slow 74HC4050 level shifters.

                          I made provision for extra capacitance next to the ADCs, although this makes no difference.

                          I didn't try a ferrite bead yet nor separate 7805s for analog and digital sides as yet, and yes I do see the strange shadowing mentioned.

                           

                          At first I thought I might be getting better results, but really they're not a lot better.

                          I will probably try a few more experiments, using comments from here, and depending on what I find, possibly do another board iteration.

                          For my hobby related purposes, the quality may not be great, but the video is certainly of recognisable quality.

                           

                          VGA Videowall now has the new design, including photos and videos of results.

                           

                          Thanks to everyone who has provided suggestions.

                           

                          {{{ Andy

                            • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                              andykey

                              Replacing 0R resistors with ferrite beads didn't help.

                              Nor did more capacitance around the OpAmps / ADCs.

                              My next iteration will have (listed in order of most likely to make a difference first)

                              1. completely separate power for analog and digital side, including seperate 7805s, separate 0V rails (and use of 0R resistors to keep them apart, other than the point where 0V enters the board)
                              2. 74LVC244A level shifters, which are much faster
                              3. sync signals through these new level shifters (fixing an error in the prior attempt), removing any variability where hsync is detected
                              4. possibly ferrite core and/or ferrite beads in place of certain 0R resistors - at this point I've yet to work out what ferrite core might be a good choice

                              Latest VGAVW circuit

                              I wonder if this will be enough to improve things...

                               

                              {{{ Andy

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                                • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                                  shabaz

                                  Hi Andy,

                                   

                                  The fact that the noise is present on the top three bits means there is a severe issue, that may be logic related. If the supply and op amps are not misbehaving (i.e. there's no oscillations and you've got the recommended capacitors directly across the supply rails) then there's a high chance it is the level shifter delay.. that should be the first thing to modify.

                                  However, personally I'd spend some time really examining the output for different (simple) stimulus test images, to see if there is a pattern to the noise. You've not provided any screenshots of it.

                                  The few times I've had digital issues with image capture (from cameras in my case), I was able to narrow down the problem by looking for a pattern, despite it originally just looking like random noise.

                                    • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                                      andykey

                                      Good points.

                                       

                                      I don't think the OpAmps or ADCs are misbehaving, and I have tried additional decoupling around them.

                                       

                                      The level shifter is only used for centronics (not relevant here) and passing hsync and vsync (not timing sensitive so no problem either) to the CMod.

                                      The fact the level shifters are slow means that the FPGA might think the picture starts a pixel or two too late, which might manifest itself as sideways wobble or tear, but not so much as noise.

                                      The FPGA clocks the ADCs and samples the output according to that same clock.

                                      RGB data does not go through level shifters or any buffer that might add a delay before hitting the FPGA. I believe I removed this potential source of trouble last board iteration.

                                       

                                      The circuit can be thought of in peices

                                      1. video capture using ADC
                                      2. picture rearrangment using CMod/FPGA combination
                                      3. video output using resistor DAC

                                       

                                      I think I have 2 kinds of noise.

                                      • Consider a 256 shades of grey testcard. I might reasonably expect that to be quantized into 8 bands. I actually see noise near the edges between bands. This suggests that maybe the noise isn't in all the top 3 bits - perhaps its now just the lowest of the three. This noise comes from the input ADC side of the circuit because when the videowall displays the sampled image scaled and/or translated, the speckled noisy pixel are also scaled and/or translated. I wonder if noise from the digital part of the circuit is feeding back into the analog 5V or 0V rails used by the video capture part. I tried ferrite beads, but I think I need ones that become resistive at lower frequencies for them to be effective. I hope that using separate power circuits (7805s and capacitors) and a separate 0V return rail for analog and digital sides might help with this
                                      • The videowall samples one full size image whilst displaying scaled and/or translated portions of the previous one (which is its key functional purpose).  The original full size image being sampled is faintly visible in the scaled and/or translated one being displayed. I have to wonder if somehow the signal from the input ADC side of the circuit is affecting the output DAC side of the circuit. Or, could the voltages coming out of the FPGA be not be clean, and instead be affected by signals going in to the FPGA elsewhere? This might suggest I need to put the output RGB through some kind of buffer, and then through the resistor DAC.

                                       

                                      VGA Videowall does have a couple of MPEG videos showing picture quality, one using greyscale testcards from google image search, towards the end in the testing section.

                                       

                                      You're right that I can probably learn more with carefully crafted testcards, and even doing tricks like taking the output of the ADCs and putting it directly to the DACs.

                                       

                                      Thanks for the tip. Hopefully I can try a few more next weekend.

                                       

                                      {{{ Andy

                                        • Re: AD9057, a circuit like the Evaluation Board, sources of noise
                                          nickgray

                                          Hello, Andy -

                                           

                                          I was wondering if you ever got your circuit working correctly. You have some very good suggestions from many people, but I do have some suggestions.

                                           

                                          As someone already mentioned, the potentiometers can add noise to your system. In addition to that, with almost no current trough the wiper of the pot, a varnish will eventually build up around the wiper contact, resulting in an open circuit on either side of the wiper, making it impossible to make small adjustments to the pot. It would be better to use precision resistors for setting the gain of the amplifiers. Besides, with the values you have chosen for the amplifier gain setting resistors and the pot, tolerance of these components would not allow proper setting of the amplifier under all tolerance conditions.

                                           

                                          The gain of the circuit you have needs to be dynamic. That is, the gain needs to change as the input value changes. Doesn’t make sense? Consider the facts: Your gain is inverting, so 0V input needs to become 2.5V (ADC reference voltage) at the ADC input and 0.7V input needs to become 0V at the ADC input. Recall that the inverting input of the amplifier is at Vref/2 =  1.25V. This means that, with 0V input and the input, the amplifier gain must be unity, producing an amplifier output of 2.5V. The result is that the amplifier output when the input is 0.7V would be 1.8V. The result is a very narrow 3-digit ADC output code range of 111 down to 101 and the only output codes you would see are 101, 110 and 111, when the code range should be 111 down to 000. Regardless of the amplifier gain, the amplifier output will never get even close to 0V!

                                           

                                          You have two options, as I see it. You can go with a non-inverting configuration with a gain of 2.5V / 0.7V = 3.57 (you should not provide a bias voltage at the amplifier non-inverting input). This means the sense of the ADC output signal would be inverted compared with your current circuit. Your other option is to use a dual op-amp configured as non-inverting stage, followed by an inverting, level shifting stage for each of the three inputs. I suggest that the first amplifier operate with a gain of Vref / 0.7 = 2.5 / 0.7 = 3.57. Because high value resistors produce more noise than do lower values, I suggest keeping resistor values as low as reasonable. I suggest setting the input resistors to 1.07k, 1% and setting the gain feedback resistors to 2.74k, 1%. (Recall that non-inverting gain = 1 + Rf/Rg.) Set the gain and feedback resistors of the second stage to the same value between 1k and 5k, both 1% values. The divider resistors at the non-inverting input of the second stage should be equal value 1% resistors of up to 10k. Add a 0.1uF ceramic capacitor at the non-inverting input of the second amplifier.

                                           

                                          Other suggestions: Eliminate R18 as this prevents a low (AC) impedance to the ground plane. Be sure that each op-amp and ADC power pin has a 0.1uF ceramic bypass capacitor as close to the package as possible. Add capacitors in parallel with each amplifier feedback resistor such that Max Fin = 0.5 / ( 2 * pi * R * C ), where Max Fin is the maximum input frequency to the op-amp, R is the amplifier feedback resistor in Ohms and C is the added feedback capacitor in Farads. The reason for the 0.5 rather that 1 is to avoid phase distortion at higher input frequencies.

                                           

                                          Best of luck!

                                           

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