Kind of answering my own Question #1 as I dig deeper.
"performance characterization" listed for below link is pretty much a joke.
The 2A limit on phase A is already not going to work with core rails anyway.
I guess at this level, I just need to buy the PMIC eval board and do the homework.
I wonder what the thought insight behind IR38063MTR instead of TDA21240. 5A extra margin and SMBUS support?
The IRPS5401 and IR38063 feature full telemetry. I worked with Infineon to create a series of reference designs that would support a wide range of applications, with all the configurations preprogrammed and selectable via addressing on the board. The efficiency on these devices is admittedly not the best, but the full PMBus support with telemetry, real time control, small footprint and low cost are hard to beat. If you don't need or want telemetry and power mode control then there are certainly more efficient options. To summarize, efficiency was not the primary objective on this project. I architected the original design around these parts so if you have any other questions on it please feel free to reach out to me. I also put together a blog that talks about these designs if you want to check that out. There are a couple of video demos of the tool as well. Benefits of Power System Telemetry Using PMBus
Thank you for sharing the inner thought process of the design - your points were what I also suspected/agree but wanted to confirm.
I'll check out your link. As usual (micro/picozed), you guys are awesome.
As for question #2, What would be your recommendation if we are not using VCU at all?
correct - if you aren't going to ever use the VCU you can tie it to GND. Sorry for the delay.
Gurus of the forum,
I'm in a process of moving on from the SOM and branching off to our own board.
Avnet's ZU7 based UltraZed-EV reference design seems to be a variant of dual configs recommended by UG583, infineon PMICs - IRPS4501.
The listed options are from Infineon, TI, MPS.
Infineon IRPS4501 config4/6 definitely has all the good bells and whistles (740mm^2 vs TI's 1040mm^2 real estate) but has a horrendous RDSon of 145mOhm for its upper FET.
I know that efficiencies are very load specific, but most PMIC solution app notes would flex their efficiency metric muscles. It scares me that none of their eval module/datasheet for IRPS4501 lists any efficiency performance data, only ripple control specs on scope captures.
Looks like SOM design bypasses this issue by using another buck with 4~1.8mOhm, but it probably was mostly from increasing the current capacity as well.
Does Ultrazed team have any design tribal knowledge that would help me in this matter? Can you share SOM PMIC's efficiency charts if any?
I've been going through ZU5's power consolidation suggestion UG583 and looking at "always on" case#1 scenarios.
for EV, xilinx UG583 has VCU 0.9V supply as required, even if we are not using it and XPE estimates no current usage.
In this case, do we still need to power VCCINT_VCU? Perhaps just a simple LDO will be enough with no serious load?