4 Replies Latest reply on Jul 4, 2019 3:51 AM by blelly_pie

    Debugging with ILA Core




      I am a total beginner wit fpga, and the last few das, I've been fiddling with the ZedBoard, and following some exercices on how to program the PL.


      The current exercise consist of adding a binary counter and monitoring it's output via an ILA IP (cf Schma) (I didn't change anything and just copied the block diagram

      The Bitstream is generated without eror, and I can program the card, but the issue arrive when I try to look à the probe output, I get this error message int the tcl console:


      INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.

      WARNING: [Labtools 27-3361] The debug hub core was not detected.


      1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.

      2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.

      For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).

      WARNING: [Labtools 27-3413] Dropping logic core with cellname:'Zynq_i/ila_0' at location 'uuid_DF5D93A22A4E59DE8D60AFA4B2F66593' from probes file, since it cannot be found on the programmed device.



      Edit:  I also have these two messages in the flow report

      WARNING: [IP_Flow 19-3452] Invalid long/float value '1e+08' specified for parameter 'FREQ_HZ(signal_clock)' for Zynq_ila_0_0.

      WARNING: [IP_Flow 19-3452] Invalid long/float value '1e+08' specified for parameter 'FREQ_HZ(clk_intf)' for Zynq_c_counter_binary_0_1.

      Could you help me to fix this bug