I own an Digilent Avnet Zedboard (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D). This is an older version of the zedboard. Can anyone upload the master *.XDC file for this specific board? I looked at the master *.XDC files available at this website and I believe that it is incompatible with my specific development kit. Is Silica Avnet, Xilinx, or Digilent, supposed to make this file available to the public. I checked the website, GitHub, however, it appears that the file is missing.
The correct file should match, (or be very similar to), the file made reference to on page 34 of the Silica Avnet Vivado tutorial that I have attached.